Wrong data transmitted from FPGA via SPI to CM7

wissemBenjeddou — Wed, 28 Jan 2026 15:17:23 GMT

Hello everyone,

I'm using imx8mp phytec SOM. Im trying to read 48Bytes from my FPGA via SPI .

Received data:
0x 1 0x FF 0x FF 0x FF 0x FF 0x FF 0x FF 0x FF
0x FF 0x FE 0x FF 0x FF 0x 3 0x 1 0x FF 0x FF
0x FF 0x FF 0x FF 0x FF 0x FF 0x FF 0x FE 0x 0
0x 1 0x 3 0x 1 0x FF 0x FF 0x FF 0x FF 0x FF
0x FF 0x FF 0x FF 0x FE 0x 0 0x 1 0x 3 0x 1
0x FF 0x FF 0x FF 0x FF 0x FF 0x FF 0x FF 0x FF

The CS goes low only for once cycle than goes again high, i.e each byte Im reading is actually the first byte from the packet. I tried also 32 bits but this is the maximum. I want to read 384 bits (48 Bytes )with one transfer. main.c

int main(void)

{

uint32_t errorCount;

uint32_t i;

sdma_config_t sdmaConfig;

/* M7 has its local cache and enabled by default,

* need to set smart subsystems (0x28000000 ~ 0x3FFFFFFF)

* non-cacheable before accessing this address region */

BOARD_InitMemory();

/* Board specific RDC settings */

BOARD_RdcInit();

BOARD_InitBootPins();

BOARD_BootClockRUN();

BOARD_InitDebugConsole();

/* Init the SDMA module */

SDMA_GetDefaultConfig(&sdmaConfig);

SDMA_Init(DRIVER_MASTER_SPI_DMA_BASE, &sdmaConfig);

CLOCK_SetRootMux(kCLOCK_RootEcspi2, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */

CLOCK_SetRootDivider(kCLOCK_RootEcspi2, 8U, 10U); /* Set root clock to 800MHZ / 10 = 80MHZ */

PRINTF("This is ECSPI CMSIS SDMA loopback transfer example.\r\n");

PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n");

/*DSPI master init*/

DRIVER_MASTER_SPI.Initialize(ECSPI_MasterSignalEvent_t);

DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL);

DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER |ARM_SPI_CPOL0_CPHA0 |ARM_SPI_SS_MASTER_HW_OUTPUT, TRANSFER_BAUDRATE);

for (i = 0U; i < TRANSFER_SIZE; i++) {

masterTxData[i] = i; // or actual payload

}

isTransferCompleted = false;

PRINTF("Start transfer...\r\n");

/* Start master transfer */

DRIVER_MASTER_SPI.Transfer(masterTxData, masterRxData, TRANSFER_SIZE);

/* Wait slave received all data. */

while (!isTransferCompleted)

{

}

// memcpy(&spiData, masterRxData, sizeof(ibe_spi_input_data_t));

// // Print it

PRINTF("\r\nTransfer completed!");

PRINTF("\r\nTransfer completed!\r\nReceived data:\r\n");

for (i = 0U; i < TRANSFER_SIZE; i++)

{

PRINTF("0x%08X ", masterRxData[i]);

if ((i + 1) % 8 == 0) // Print 8 values per line

{

PRINTF("\r\n");

}

DRIVER_MASTER_SPI.PowerControl(ARM_POWER_OFF);

DRIVER_MASTER_SPI.Uninitialize();

while (1)

{

}

* SPDX-License-Identifier: BSD-3-Clause

#include "fsl_device_registers.h"

#include "fsl_debug_console.h"

#include "pin_mux.h"

#include "clock_config.h"

#include "board.h"

#include "fsl_ecspi_cmsis.h"

/*******************************************************************************

* Definitions

******************************************************************************/

#define DRIVER_MASTER_SPI Driver_SPI2

#define DRIVER_MASTER_SPI_DMA_BASE SDMAARM1

#define EXAMPLE_MASTER_SPI_BASE ECSPI2

#define TRANSFER_SIZE 48U

#define TRANSFER_BAUDRATE 1000000U /*! Transfer baudrate - 500k */

/*******************************************************************************

* Prototypes

******************************************************************************/

/* ECSPI user SignalEvent */

void ECSPI_MasterSignalEvent_t(uint32_t event);

/*******************************************************************************

* Variables

******************************************************************************/

AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t masterRxData[TRANSFER_SIZE], 4) = {0};

AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t masterTxData[TRANSFER_SIZE], 4) = {0};

volatile bool isTransferCompleted = false;

SPI config: 10MHz, Mode: 00 . I tried it with interrupt and now with DMA:

static int32_t ECSPI_SDMATransfer(const void *data_out,

void *data_in,

uint32_t num,

cmsis_ecspi_sdma_driver_state_t *ecspi)

{

int32_t ret;

status_t status;

ecspi_transfer_t xfer = {0};

// uint32_t datawidth =

// (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;

// uint32_t conreg = ecspi->resource->base->CONREG;

ecspi->resource->base->CONREG &= ~ECSPI_CONREG_BURST_LENGTH_MASK;

ecspi->resource->base->CONREG |= ECSPI_CONREG_BURST_LENGTH(384U); // 48 bytes

xfer.txData = (uint32_t *)data_out;

xfer.rxData = (uint32_t *)data_in;

xfer.dataSize = 48;// num * ((datawidth + 8U) / 8U);

xfer.channel = kECSPI_Channel0;

/* Configure the channel to be used. */

switch (ecspi->resource->instance)

{

case 1:

#if defined(RTE_SPI1_TRANSFER_CHANNEL)

xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;

#endif

break;

case 2:

#if defined(RTE_SPI2_TRANSFER_CHANNEL)

xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;

#endif

break;

case 3:

#if defined(RTE_SPI3_TRANSFER_CHANNEL)

xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;

#endif

break;

default:

/* Avoid MISRA 16.4 violations. */

break;

}

if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)

{

status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);

}

else

{

status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);

}

switch (status)

{

case kStatus_Success:

ret = ARM_DRIVER_OK;

break;

case kStatus_InvalidArgument:

ret = ARM_DRIVER_ERROR_PARAMETER;

break;

case kStatus_ECSPI_Busy:

ret = ARM_DRIVER_ERROR_BUSY;

break;

default:

ret = ARM_DRIVER_ERROR;

break;

}

return ret;

}

Any help will be appreciated.

Re: Wrong data transmitted from FPGA via SPI to CM7

Manuel_Salas — Thu, 09 Apr 2026 02:14:46 GMT

Hello @wissemBenjeddou

I hope you are doing very well.

Looking at the reference Manual of the i.MX8MP, I could see the SS_CTL register:

According to the BURST_LENGTH register, the number of bits shifted out is n = BURST_LENGTH + 1:

So, you can try to change:

From:

ECSPI_CONREG_BURST_LENGTH(384U)

To:

ECSPI_CONREG_BURST_LENGTH(383U)

Best regards,

Salas.

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Wrong data transmitted from FPGA via SPI to CM7

Re: Wrong data transmitted from FPGA via SPI to CM7