topic PCF85134HL software help in Other NXP Products

PCF85134HL software help

Vaib_16 — Fri, 23 Jan 2026 07:20:32 GMT

I need assistance with the software driver implementation for the PCF85134HL LCD driver IC.
Is there any reference template or sample driver available for this device?

If not, I would appreciate clarification on the following points.
I am using atmega2560

Before initialization, the LCD driver remains in its default state with 1:4 multiplex, 1/3 bias, and display disabled, during which all COM and SEG pins remain at VLCD. Once the display is enabled, I would like to confirm whether the COM and SEG pins should vary with time and not remain at a constant voltage.

In my case, after enabling the LCD:

COM1, COM2, and COM4 remain at approximately 1 V
COM3 remains at approximately 3 V
All SEG pins remain at 0 V

I have verified these levels using both an oscilloscope and a multimeter, and the voltages do not change over time.

Could you please confirm whether this behavior is expected, or if the COM and SEG pins should exhibit different (time-varying) waveforms when the LCD is enabled?

Your guidance on this would be greatly appreciated. Thank you for your support.

@ SOFTWARE @PCF85134HL @PCF85134 @LCDDRIVER

Re: PCF85134HL software help

TomasVaverka — Fri, 23 Jan 2026 08:37:14 GMT

Hello Vai,

Unfortunately we do not have an official reference driver for PCF85134HL. The device is also in the EoL status, so I can only offer limited support at this time.

About the waveforms: after initialization and when the display is enabled with a valid clock, both COM (BPx) and SEG (Sx) pins output time‑varying AC waveforms per the selected multiplex/bias, they should not remain at a fixed DC level. At power‑on, the device defaults to display disabled and forces all COM/SEG to VLCD, you must send a MODE‑SET (E=1) and write display RAM. Also note, a clock is mandatory. Without it, the LCD can freeze in a DC state.

Your measurements suggest the display is still disabled, the clock is not running, VLCD is not present, or the I²C command sequence did not complete. Please verify: (1) VLCD and VDD are both applied (per datasheet), (2) OSC pin strapping is correct and a clock is present, (3) you send MODE‑SET with E=1, then DEVICE‑SELECT, LOAD‑DATA‑POINTER, and data, and (4) address pins match the commands. For scope checks, measure SEG–to–BP (AC‑coupled) rather than node‑to‑GND.

BRs, Tomas

Re: PCF85134HL software help

Vaib_16 — Fri, 23 Jan 2026 09:50:16 GMT

Thanks Tomas, for your response.

You mentioned that the clock is mandatory. In my case, I am using the internal clock as per the datasheet.

I have connected the OSC pin to VSS, and the CLK pin is connected to ground (VSS) through a 100 k resistor and when i checked the CLK pin in oscilloscope , I could see clk pulse. However, connecting the CLK pin to ground is not explicitly mentioned in the datasheet, so I would appreciate it if you could kindly clarify whether this configuration is correct or any particular pin i should connect that to.

Regarding the points you asked about:

VLCD and VDD are both connected to 3 V
The OSC pin is connected to VSS

Please let me know if any additional information is required.

Additionally, I tried changing the multiplex settings, but in all configurations the COM pins remained at static DC levels; however, the issue observed on COM3 shifted to the corresponding COM line based on the selected multiplex configuration. The SEG pins also remained static and did not exhibit any time-varying behavior.

@TomasVaverka @software @pcf85134

Re: PCF85134HL software help

TomasVaverka — Fri, 23 Jan 2026 10:53:09 GMT

Hello Vai,

Your OSC = VSS connection is correct for using the internal oscillator. In this mode, CLK becomes an output that the device presents to the outside world (so it can be used to clock other cascaded LCD drivers).

The fact that your “COM3 issue shifts when you change multiplex mode” is a good clue. It shows the MODE‑SET bits for multiplex are being applied, but the backplane waveform generation is still not active, typically because E=0 (display disabled) or the clock was effectively loaded/suppressed by the 100k to GND on CLK.

BRs, Tomas