Other NXP ProductsのトピックRe: A5M36TG140_Biasing Sequence

A5M36TG140_Biasing Sequence

joshlim — Wed, 21 Jan 2026 23:52:40 GMT

I am writing to inquire about a product-related matter that we would like to clarify.

According to the datasheet (page 7), under the Correct Biasing Sequence – Turn ON section, the following sequence is described:

GaN TR bias setting
LDMOS bias setting

However, our current biasing sequence is as follows:
LDMOS bias setting (80 mA / 40 mA)
GaN peaking voltage setting
Apply 50 V and then set GaN carrier bias
Apply RF signal

We would like to ask the manufacturer whether this biasing sequence could potentially have any impact on GaN TR reliability or damage.

Your confirmation would be greatly appreciated.

Thank you for your support.

Josh

Re: A5M36TG140_Biasing Sequence

ErikaC — Thu, 22 Jan 2026 17:23:08 GMT

Hello!

The proposed biasing sequence applies the GaN drain voltage before explicitly turning the GaN gate fully off.
This approach may work in systems that include additional hardware protection, but it is not the sequence recommended in the A5M36TG140 datasheet.
The sequence described in the datasheet ensures that the GaN device is completely turned off before any high drain voltage is applied. This helps prevent unintended drain current, reduces electrical stress, and protects the device from long‑term damage.

Any biasing or de‑biasing sequence that differs from the datasheet recommendation is outside the specified operating conditions and must be carefully reviewed and validated at the system level, since correct operation and long‑term reliability are not guaranteed.

Re: A5M36TG140_Biasing Sequence

joshlim — Sun, 01 Feb 2026 11:10:19 GMT

Hello,

Thank you for your suppor.

Regards,

Josh