Other NXP ProductsのトピックUnable to handle kernel paging request at virtual address ffffffffd034001f

Unable to handle kernel paging request at virtual address ffffffffd034001f

Bhardwaj — Mon, 05 Jan 2026 12:57:33 GMT

Hi,

We are working with a custom i.MX8M Plus DDR4 board that includes 32 MB QSPI NOR flash.
Our objective is to boot U-Boot, Linux kernel, device tree, and initramfs (rootfs.img) entirely from QSPI flash, without using SD/eMMC.

We are able to successfully boot up to U-Boot (flash.bin) from QSPI flash in custom but it is hangs in kernel.

Generated images for I.MX8MPLUS LPDDR4 EVK (flash.bin,image.gz ,imx8mp-evk.dtb and rootfs.img) that's working fine.

U-Boot Environment Setup

After booting into U-Boot from QSPI, we configure the following environment variables to load the kernel, device tree, and initramfs from flash:

sf probe 0
setenv loadaddr 0x40480000 // kernel
setenv fdt_addr 0x43000000 //dtb
setenv initrd_addr 0x43800000 //rootfs (minimal initramfs)
setenv kernel_comp_addr_r 0x50000000
setenv kernel_comp_size 0x04000000

Reading Images from QSPI Flash

sf read ${loadaddr} 0x0024D000 0x00E59A6F
sf read ${fdt_addr} 0x010A6B00 0x00014BBA
sf read ${initrd_addr} 0x010BB800 0x00C04DB0

Boot Command

setenv bootargs setenv bootargs "console=ttymxc1,115200 earlycon root=/dev/ram0 rw rdinit=/sbin/init loglevel=8"

booti ${loadaddr} ${initrd_addr} ${fdt_addr}

After this kernel starting But getting error also attaching the error logs:

Unable to handle kernel paging request at virtual address ffffffffd034001f

but sometimes we are able to get till initramfs.

Attaching the defconfig and dts in kernel (linux-imx) also attaching the logs that hangs in kernel.

Re: Unable to handle kernel paging request at virtual address ffffffffd034001f

Manuel_Salas — Mon, 05 Jan 2026 21:15:12 GMT

Hello @Bhardwaj

I hope you are doing very well.

Do you already have a DDR Stress Test report for your exact DDR4 part and layout?

If yes, can you share the key results and the SPL ddr4_timing you generated?

Best regards,

Salas.

Re: Unable to handle kernel paging request at virtual address ffffffffd034001f

Bhardwaj — Wed, 21 Jan 2026 17:50:14 GMT

Hi @Manuel_Salas ,

Thank you for Support , i am successfully boot the kernel and initrams.

Now i am facing on Ethernet phy not linking .

Working on a custom i.MX8M Plus DDR4 board and facing an issue with Ethernet PHY link-up.

Hardware details:

SoC: i.MX8M Plus
PHY: Marvell 88E1512
Interface: RGMII-ID
Board: Custom design

Issue description:
I am unable to bring up the Ethernet PHY link. While probing the PHY clocks using an oscilloscope:

TX_CLK = 125 MHz
RX_CLK = 125 MHz

So the PHY clocks appear to be present and stable, but the PHY link does not come up and I am unable to ping the PHY.

Also attached the Kernel log for reference.

Steps performed:

mount -t proc proc /proc

mount -t sysfs sysfs /sys

mount -t devtmpfs devtmpfs /dev

ifconfig eth1 192.168.5.1 up

[ 54.807828] imx-dwmac 30bf0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0

[ 54.815831] imx-dwmac 30bf0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1

[ 54.823833] imx-dwmac 30bf0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2

[ 54.831900] imx-dwmac 30bf0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3

[ 54.839831] imx-dwmac 30bf0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-4

[ 54.892291] imx-dwmac 30bf0000.ethernet eth1: PHY [stmmac-1:01] driver [Marvell 88E1510] (irq=POLL)

[ 54.901504] imx-dwmac 30bf0000.ethernet eth1: No Safety Features support found

[ 54.908774] imx-dwmac 30bf0000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported

[ 54.917533] imx-dwmac 30bf0000.ethernet eth1: registered PTP clock

[ 54.924316] imx-dwmac 30bf0000.ethernet eth1: configuring for phy/rgmii-id link mode

[ 54.932963] 8021q: adding VLAN 0 to HW filter on device eth1

The above procedure working on i.MX8MPLUS EVK and able to ping the PHY.

Observations / Questions:

PHY clocks are present (125 MHz TX/RX).
PHY driver is detected, but link never comes up.
Is there any known device tree, strap configuration, or RGMII delay requirement specific to Marvell 88E1512 on i.MX8M Plus?
Any recommended PHY register checks or debug steps to further isolate the issue?

Any guidance or pointers would be greatly appreciated.

Thanks in advance.