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    <title>topic Re: cache control register mpc5644a in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/cache-control-register-mpc5644a/m-p/310522#M3029</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Cache is a part of e200z4 core and so configuration registers are described in core reference manual, chapter 9:&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/e200z4RM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/e200z4RM.pdf&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 07 Apr 2014 13:09:32 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2014-04-07T13:09:32Z</dc:date>
    <item>
      <title>cache control register mpc5644a</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/cache-control-register-mpc5644a/m-p/310521#M3028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Does MPC5644A have a cache control unit?&lt;/P&gt;&lt;P&gt;I see some settings mentioned on chapter 6 of its reference manual?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I do not see any cache control unit or a register definition for that.&lt;/P&gt;&lt;P&gt;I do not see that when I load the code and view the register listings with the debugger.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;izzet&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Apr 2014 05:58:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/cache-control-register-mpc5644a/m-p/310521#M3028</guid>
      <dc:creator>izzetozcelik</dc:creator>
      <dc:date>2014-04-04T05:58:34Z</dc:date>
    </item>
    <item>
      <title>Re: cache control register mpc5644a</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/cache-control-register-mpc5644a/m-p/310522#M3029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Cache is a part of e200z4 core and so configuration registers are described in core reference manual, chapter 9:&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/e200z4RM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/e200z4RM.pdf&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Apr 2014 13:09:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/cache-control-register-mpc5644a/m-p/310522#M3029</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2014-04-07T13:09:32Z</dc:date>
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