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    <title>Other NXP Products中的主题 Boot Manager interface to SP processor not working for MCU3 VDK</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/Boot-Manager-interface-to-SP-processor-not-working-for-MCU3-VDK/m-p/2181241#M30275</link>
    <description>&lt;P&gt;Hi all,&lt;BR /&gt;&lt;SPAN&gt;I'm working on GM SW based on GRAYVIP 22 with HSE FW&amp;nbsp;s32n5_gp_fw_1.1.8_0.19.0_pb250801 This Software implements the boot manager and boot loader code. Loading the envelop1 bin, i am able to see the correct value in the memory area.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 471px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/359757i78D19EB935C85D48/image-dimensions/471x346?v=v2" width="471" height="346" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;DIV class=""&gt;After this, the boot manager on CRS executed the&amp;nbsp; &lt;EM&gt;FBL_Port_BM_InitializeInterface&lt;/EM&gt;() function that is used to establish an interface to SP processor.&lt;BR /&gt;Inside this function, there is a do-while loop that needs a specific response of SP to continue and itis never satisfied until the elapsed time is not reached, because the &lt;EM&gt;FBL_BM_SPResponse&lt;/EM&gt; is always 0xFF.&lt;BR /&gt;&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (9).png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/359758iA3C545CFCCAF5BC5/image-size/large?v=v2&amp;amp;px=999" role="button" title="image (9).png" alt="image (9).png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;BR /&gt;Do you have any hints?&lt;BR /&gt;I can share the reproducer&amp;nbsp;&lt;/DIV&gt;</description>
    <pubDate>Tue, 07 Oct 2025 13:58:58 GMT</pubDate>
    <dc:creator>Luca_Fodale</dc:creator>
    <dc:date>2025-10-07T13:58:58Z</dc:date>
    <item>
      <title>Boot Manager interface to SP processor not working for MCU3 VDK</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Boot-Manager-interface-to-SP-processor-not-working-for-MCU3-VDK/m-p/2181241#M30275</link>
      <description>&lt;P&gt;Hi all,&lt;BR /&gt;&lt;SPAN&gt;I'm working on GM SW based on GRAYVIP 22 with HSE FW&amp;nbsp;s32n5_gp_fw_1.1.8_0.19.0_pb250801 This Software implements the boot manager and boot loader code. Loading the envelop1 bin, i am able to see the correct value in the memory area.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 471px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/359757i78D19EB935C85D48/image-dimensions/471x346?v=v2" width="471" height="346" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;DIV class=""&gt;After this, the boot manager on CRS executed the&amp;nbsp; &lt;EM&gt;FBL_Port_BM_InitializeInterface&lt;/EM&gt;() function that is used to establish an interface to SP processor.&lt;BR /&gt;Inside this function, there is a do-while loop that needs a specific response of SP to continue and itis never satisfied until the elapsed time is not reached, because the &lt;EM&gt;FBL_BM_SPResponse&lt;/EM&gt; is always 0xFF.&lt;BR /&gt;&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (9).png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/359758iA3C545CFCCAF5BC5/image-size/large?v=v2&amp;amp;px=999" role="button" title="image (9).png" alt="image (9).png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;BR /&gt;Do you have any hints?&lt;BR /&gt;I can share the reproducer&amp;nbsp;&lt;/DIV&gt;</description>
      <pubDate>Tue, 07 Oct 2025 13:58:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Boot-Manager-interface-to-SP-processor-not-working-for-MCU3-VDK/m-p/2181241#M30275</guid>
      <dc:creator>Luca_Fodale</dc:creator>
      <dc:date>2025-10-07T13:58:58Z</dc:date>
    </item>
    <item>
      <title>Re: Boot Manager interface to SP processor not working for MCU3 VDK</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Boot-Manager-interface-to-SP-processor-not-working-for-MCU3-VDK/m-p/2181825#M30290</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Could you specify what&amp;nbsp; is SP?&lt;/P&gt;
&lt;P&gt;if there is no response from SP then check&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;
&lt;P&gt;Verify SP Firmware Boot&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Use a debugger or trace to confirm SP is alive and executing code.&lt;/LI&gt;
&lt;LI&gt;Check if SP is stuck in a reset or waiting for a trigger.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Log or Trace SP Behavior&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;If possible, add logging or breakpoints in SP code to see if it receives any request or command from CRS.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Review Boot Manager Expectations&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Look into the documentation or source code to understand what FBL_BM_SPResponse should be set to when SP is ready.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 08 Oct 2025 11:45:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Boot-Manager-interface-to-SP-processor-not-working-for-MCU3-VDK/m-p/2181825#M30290</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2025-10-08T11:45:58Z</dc:date>
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