https://community.nxp.com/t5/Other-NXP-Products/LX2160A-Processor-Errors/m-p/2160926#M29864 <P>Hello,</P> <P>each interrupt ID corresponds to a cluster,</P> <P>the LX2160A has a Sixteen 32-bit/64-bit Arm v8 A72 CPUs arranged as clusters of two cores sharing a 1 MB L2 cache, it means if there is any error on one core the assigned cluster will trigger the corresponding interrupt, those interrupts&nbsp;<SPAN>are ORed and connected to GIC at the mentioned ID slots, for more information about the interrupts you can refer to the ARM GIC manual.</SPAN></P> Sat, 30 Aug 2025 04:00:17 GMT Oswalag 2025-08-30T04:00:17Z https://community.nxp.com/t5/Other-NXP-Products/LX2160A-Processor-Errors/m-p/2159905#M29845 <P>Hi,&nbsp;</P><P>LX2160ARM.pdf specifies ORed error interrupts from processor clusters as Interrupt IDs 96...103.&nbsp;</P><P>Where can I find a list of errors which are ORed in these interrupt?</P><P>Thanks.</P> Thu, 28 Aug 2025 11:27:30 GMT https://community.nxp.com/t5/Other-NXP-Products/LX2160A-Processor-Errors/m-p/2159905#M29845 bboykaz 2025-08-28T11:27:30Z https://community.nxp.com/t5/Other-NXP-Products/LX2160A-Processor-Errors/m-p/2160926#M29864 <P>Hello,</P> <P>each interrupt ID corresponds to a cluster,</P> <P>the LX2160A has a Sixteen 32-bit/64-bit Arm v8 A72 CPUs arranged as clusters of two cores sharing a 1 MB L2 cache, it means if there is any error on one core the assigned cluster will trigger the corresponding interrupt, those interrupts&nbsp;<SPAN>are ORed and connected to GIC at the mentioned ID slots, for more information about the interrupts you can refer to the ARM GIC manual.</SPAN></P> Sat, 30 Aug 2025 04:00:17 GMT https://community.nxp.com/t5/Other-NXP-Products/LX2160A-Processor-Errors/m-p/2160926#M29864 Oswalag 2025-08-30T04:00:17Z