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    <title>topic Register Access in S32G-VNP-RDB32 (SJA1110) Switch in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/Register-Access-in-S32G-VNP-RDB32-SJA1110-Switch/m-p/2134136#M29326</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am looking to write the values into the Register&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;can you give me the complete address for Reading and writing&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Address Name Access Reset Description&lt;/SPAN&gt;&lt;BR /&gt;&lt;STRONG&gt;8Ch&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FFFFFFFEh)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;before&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;8ch&amp;nbsp;&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;what would be the base address?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;like for example it will have 0x3fc0008c so for this dynamic entry table we will have a complete address can you give me the complete address for&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;8Ch DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FFFFFFFEh)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;90h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;94h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY2&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;98h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;9Ch DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY4&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;A0h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY5&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;A4h DYN_BE_LKP_CTRL R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FF800000h)&lt;BR /&gt;&lt;BR /&gt;can you Provide me the full address for configuring the Dynamic Entry in the register ?&lt;BR /&gt;&lt;BR /&gt;and where this implementation need to be take place in SJA1110 Switch&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 15 Jul 2025 11:24:13 GMT</pubDate>
    <dc:creator>Atkinson</dc:creator>
    <dc:date>2025-07-15T11:24:13Z</dc:date>
    <item>
      <title>Register Access in S32G-VNP-RDB32 (SJA1110) Switch</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Register-Access-in-S32G-VNP-RDB32-SJA1110-Switch/m-p/2134136#M29326</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am looking to write the values into the Register&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;can you give me the complete address for Reading and writing&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Address Name Access Reset Description&lt;/SPAN&gt;&lt;BR /&gt;&lt;STRONG&gt;8Ch&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FFFFFFFEh)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;before&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;8ch&amp;nbsp;&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;what would be the base address?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;like for example it will have 0x3fc0008c so for this dynamic entry table we will have a complete address can you give me the complete address for&amp;nbsp;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;8Ch DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FFFFFFFEh)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;90h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;94h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY2&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;98h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;9Ch DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY4&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;A0h DYN_BE_LKP_&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENTRY5&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;A4h DYN_BE_LKP_CTRL R/W 0h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(FF800000h)&lt;BR /&gt;&lt;BR /&gt;can you Provide me the full address for configuring the Dynamic Entry in the register ?&lt;BR /&gt;&lt;BR /&gt;and where this implementation need to be take place in SJA1110 Switch&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Jul 2025 11:24:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Register-Access-in-S32G-VNP-RDB32-SJA1110-Switch/m-p/2134136#M29326</guid>
      <dc:creator>Atkinson</dc:creator>
      <dc:date>2025-07-15T11:24:13Z</dc:date>
    </item>
    <item>
      <title>Re: Register Access in S32G-VNP-RDB32 (SJA1110) Switch</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Register-Access-in-S32G-VNP-RDB32-SJA1110-Switch/m-p/2134751#M29339</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/248906"&gt;@Atkinson&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;DIV&gt;
&lt;DIV id="&amp;quot;componentDiv&amp;quot;"&gt;
&lt;P&gt;I understand it might not seem straightforward at first, but the concept is actually quite simple.&lt;/P&gt;
&lt;P&gt;The&amp;nbsp;final&amp;nbsp;register address depends on the access method - whether you're accessing it internally via the M7 core over AHB, or externally via the SPI_AP interface. The base addresses differ depending on the access point.&lt;/P&gt;
&lt;P&gt;The register address is calculated using the base address provided in Table 2 of UM11107. For example, for the switch subsystem, the base address is&amp;nbsp;&lt;STRONG&gt;0x00000000&amp;nbsp;&lt;/STRONG&gt;for SPI_AP access and&amp;nbsp;&lt;STRONG&gt;0xFF000000&amp;nbsp;&lt;/STRONG&gt;for AHB access.&lt;/P&gt;
&lt;P&gt;In your case, the register&amp;nbsp;&lt;STRONG&gt;0x8C&amp;nbsp;&lt;/STRONG&gt;(DYN_BE_LKP_ENTRY0) becomes&amp;nbsp;&lt;STRONG&gt;0xFF00008C&amp;nbsp;&lt;/STRONG&gt;when accessed via AHB.&lt;/P&gt;
&lt;P&gt;Now, here’s where it might get confusing: the SDK driver defines the following:&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;DIV&gt;#define SJA1110_L2_ART_LE_ADDR (&lt;STRONG&gt;0x3fc00023&lt;/STRONG&gt;) /**&amp;lt; Address of the l2ArtLockedEntry register *&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;The SWITCH_DRV_Write routine shifts the address left by 2 bits (&amp;lt;&amp;lt; 2) for internal (AHB) access. For SPI transfers (used in cascaded switch setups), no shift is applied. So, &lt;STRONG&gt;0x3fc00023&lt;/STRONG&gt; &amp;lt;&amp;lt; 2 results in &lt;STRONG&gt;0xFF00008C&lt;/STRONG&gt;.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;I hope that with the explanation above, it makes sense now.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Wed, 16 Jul 2025 07:47:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Register-Access-in-S32G-VNP-RDB32-SJA1110-Switch/m-p/2134751#M29339</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2025-07-16T07:47:20Z</dc:date>
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