SBC:F6500

Wen666 — Mon, 30 Jun 2025 07:17:14 GMT

Currently, I am encountering a problem related to the DIAG_SF_ERR_ADR register during the initialization of the FS6522 chip. The specific situation is as follows: after completing LBIST and ABIST1, the self-check shows "OK" and the fault count of the DIAG_SF_ERR_ADR register is 0. However, after reading the next register (regardless of which one is read), the fault count of the DIAG_SF_ERR_ADR register becomes 5. Have any of you encountered the same problem? I'm seeking an answer and haven't been able to identify the cause yet.

Re: SBC:F6500

TomasVaverka — Mon, 30 Jun 2025 10:44:45 GMT

Hi,

Does this problem happen also in Debug mode? If not, my assumption is that there is WD refresh error that increases the fault error counter in such a short time. Please try to use the initialization sequence shown in our AN5238, chapter 14.2.

BRs, Tomas

Re: SBC:F6500

Wen666 — Tue, 01 Jul 2025 06:24:42 GMT

Thanks.
It will also occur in the debugging mode. Further investigation revealed that this situation only occurs during the first run after the program is burned. After a restart, the error fault count returns to normal. The initialization process follows the manual and involves reading and writing to the registers.

Re: SBC:F6500

TomasVaverka — Wed, 02 Jul 2025 06:25:58 GMT

Hi,

Is there watchdog refresh before fault error counter readout 0? How many times ? There will be several external RSTB during MCU program that leading to fault error counter increase. So I wonder fault error counter 5 is right and 0 is not right？

To see details, please share SBC SPI commands for analysis.

BRs, Tomas

Re: SBC:F6500

Wen666 — Thu, 03 Jul 2025 00:44:43 GMT

Here is my initialization process code. During the initialization process, no reset occurred. According to the data manual, the error fault counter should be 1 in the initialization stage if no fault occurred. It should be reduced to 0 after seven correct dog-feeding operations. The dog-feeding process was normal, but the value read from the fault error counter was 5 instead of 1.

void FS65_Init(void)
{
uint8_t WDRefresh = 0;
uint32_t fs65_error_code = 0;

// 0- Get silicon version
/*fs65_error_code = FS65_UpdateRegisterContent(DEVICE_ID_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DEVICE_ID);*/

// 1- Verify
// Built-in self-test
fs65_error_code += FS65_UpdateRegisterContent(BIST_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_BIST);
if(0 == INTstruct.BIST.B.LBIST_OK)
{
FS65_ErrorCallback(); // Logic built-in self-test
}

if(0 == INTstruct.BIST.B.ABIST1_OK)
{
FS65_ErrorCallback(); // Analog built-in self-test
}

// Verify VPRE buck or buck boost configuration
// Verify VCCA and VAUX voltage configuration (3.3 V or 5.0 V)
// Verify debug mode is not activated
// Verify deep Fail-safe configuration
fs65_error_code = FS65_UpdateRegisterContent(HW_CONFIG_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_HW_CONFIG);

// 2- Configure
// Configure VCORE, VCCA, and VAUX overvoltage and undervoltage impact on RSTB and FS0B
fs65_error_code = FS65_Set_INIT_VCCA_OVUV_IMPACT(FS65_Registers_InitValues.INIT_VCCA_OVUV_IMPACT);

fs65_error_code = FS65_Set_INIT_VCORE_OVUV_IMPACT(FS65_Registers_InitValues.INIT_VCORE_OVUV_IMPACT);

fs65_error_code = FS65_Set_INIT_VAUX_OVUV_IMPACT(FS65_Registers_InitValues.INIT_VAUX_OVUV_IMPACT);

// Configure VAUX as tracker of VCCA if using VAUX to supply sensors and VCCA as an
// MCU ADC reference voltage
fs65_error_code = FS65_Set_INIT_VREG(FS65_Registers_InitValues.INIT_VREG);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_VREG);

// Configure the WD window period and the WD counters
fs65_error_code = FS65_ChangeWDwindow(FS65_Registers_InitValues.WD_WINDOW);
FS65_Check_Error(fs65_error_code, FS65_errorcode_WD_WINDOW);

// Configure the final and indirectly intermediate value of the fault error counter
fs65_error_code = FS65_Set_INIT_WD_CNT(FS65_Registers_InitValues.INIT_WD_CNT);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_WD_CNT);

// Configure the WD impact on RSTB and FS0B
fs65_error_code = FS65_Set_INIT_SF_IMPACT(FS65_Registers_InitValues.INIT_SF_IMPACT);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_SF_IMPACT);

// Configure RSTB and FS0B behavior when fault error counter intermediate value
fs65_error_code = FS65_Set_INIT_FAULT(FS65_Registers_InitValues.INIT_FAULT);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_FAULT);

// Configure the RSTB pulse duration
// Configure MCU FCCU error monitoring in regards to IO[2] and IO[3] connections
// Configure Ext. IC error monitoring in regards to IO[4] and IO[5] connections
fs65_error_code = FS65_Set_INIT_FSSM(FS65_Registers_InitValues.INIT_FSSM);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_FSSM);

fs65_error_code = FS65_Set_INIT_WU1(FS65_Registers_InitValues.INIT_WU1);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_WU1);

fs65_error_code = FS65_Set_INIT_WU2(FS65_Registers_InitValues.INIT_WU2);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_WU2);

// 3- Execute
// Execute ABIST2 on VAUX by the SPI request from the MCU
fs65_error_code = FS65_UpdateRegisterContent(INIT_VAUX_OVUV_IMPACT_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_VAUX_OVUV_IMPACT);
if((INTstruct.INIT_VAUX_OVUV_IMPACT.B.VAUX_FS_OV) || (INTstruct.INIT_VAUX_OVUV_IMPACT.B.VAUX_FS_UV))
{
fs65_error_code = FS65_RunABIST2_VAUX();
FS65_Check_Error(fs65_error_code, FS65_errorcode_ABIST2_VAUX);
}

fs65_error_code = FS65_UpdateRegisterContent(BIST_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_BIST);
if(0 == INTstruct.BIST.B.ABIST2_VAUX_OK)
{
FS65_SetLPOFFmode_autoWU();
FS65_ErrorCallback();
}

// Close the Fail-safe INIT phase
FS65_WD_Refresh();

// Close the Main INIT phase
fs65_error_code = FS65_Set_INIT_INT(FS65_Registers_InitValues.INIT_INT);
FS65_Check_Error(fs65_error_code, FS65_errorcode_INIT_INT);

// Clear all the flags by reading all DIAG registers of both Main and Fail-safe registers
// Main registers
fs65_error_code = FS65_UpdateRegisterContent(DIAG_VPRE_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_VPRE);

fs65_error_code = FS65_UpdateRegisterContent(DIAG_VCORE_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_VCORE);

fs65_error_code = FS65_UpdateRegisterContent(DIAG_VCCA_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_VCCA);

fs65_error_code = FS65_UpdateRegisterContent(DIAG_VAUX_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_VAUX);

fs65_error_code = FS65_UpdateRegisterContent(DIAG_VSUP_VCAN_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_VSUP_VCAN);

fs65_error_code = FS65_UpdateRegisterContent(DIAG_SPI_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_DIAG_SPI);

// Clear the fault error counter to "0" by seven consecutive good WD refresh
for(WDRefresh = 0; WDRefresh < 7; WDRefresh ++)
{
Loncin_Dealy_ms(1);
FS65_WD_Refresh();

// Refresh the failure error counter
fs65_error_code = FS65_UpdateRegisterContent(DIAG_SF_ERR_ADR);
}

// 6. Configure parameters for the non-init_in phase
fs65_error_code = FS65_Config_NonInit();
FS65_Check_Error(fs65_error_code, FS65_errorcode_NonInit);

// 7. Release FS0B (active high)
fs65_error_code = FS65_UpdateRegisterContent(RELEASE_FSxB_ADR);
FS65_Check_Error(fs65_error_code, FS65_errorcode_RELEASE_FSxB);

FS0B = INTstruct.RELEASE_FSxB.B.FS0B_SNS;
fs65_error_code = FS65_ReleaseFS0B();
FS65_Check_Error(fs65_error_code, FS65_errorcode_ReleaseFS0B);

// Configure the WD window period to 1024ms
fs65_error_code = FS65_ChangeWDwindow(WD_WIN_1024);
FS65_Check_Error(fs65_error_code, FS65_errorcode_WD_WINDOW);
}

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