<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32K388 RGMII in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/S32K388-RGMII/m-p/2116878#M28998</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/251582"&gt;@AB5&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;You’ll need to use level shifters. I found an interesting article on the topic: &lt;A href="https://www.nexperia.com/dam/jcr:790eaac6-e53d-4235-a3d7-4f6330fa7009/Nexperia%20Webinar%20Lost%20in%20Translation%20part%201_250522.pdf" target="_blank"&gt;https://www.nexperia.com/dam/jcr:790eaac6-e53d-4235-a3d7-4f6330fa7009/Nexperia%20Webinar%20Lost%20in%20Translation%20part%201_250522.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;For RGMII (Reduced Gigabit Media Independent Interface), the level shifters must meet specific requirements:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Low propagation delay to maintain tight timing margins (RGMII operates at 125 MHz DDR).&lt;/LI&gt;
&lt;LI&gt;Push-pull outputs (not open-drain) to support high-speed signal integrity.&lt;/LI&gt;
&lt;LI&gt;Direction-controlled or fixed-direction operation (auto-direction sensing introduces too much latency).&lt;/LI&gt;
&lt;LI&gt;Voltage translation from 3.3V to 1.8V (or vice versa, depending on PHY/SoC I/O levels).&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Device like the 74ALVC164245 from Nexperia can be a good candidate.&lt;/DIV&gt;
&lt;DIV&gt;Best regards,&lt;/DIV&gt;
&lt;DIV&gt;Pavel&lt;/DIV&gt;</description>
    <pubDate>Mon, 16 Jun 2025 10:26:51 GMT</pubDate>
    <dc:creator>PavelL</dc:creator>
    <dc:date>2025-06-16T10:26:51Z</dc:date>
    <item>
      <title>S32K388 RGMII</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/S32K388-RGMII/m-p/2116438#M28987</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We want to connect the S32K388 RGMII interface to an ASIC RGMII interface in a MAC to MAC connection.&amp;nbsp;&lt;/P&gt;&lt;P&gt;The S32K388 RGMII is 3.3V while the ASIC is 1.8V. Any idea how to resolve this?&lt;/P&gt;</description>
      <pubDate>Sun, 15 Jun 2025 10:59:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/S32K388-RGMII/m-p/2116438#M28987</guid>
      <dc:creator>AB5</dc:creator>
      <dc:date>2025-06-15T10:59:08Z</dc:date>
    </item>
    <item>
      <title>Re: S32K388 RGMII</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/S32K388-RGMII/m-p/2116878#M28998</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/251582"&gt;@AB5&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;You’ll need to use level shifters. I found an interesting article on the topic: &lt;A href="https://www.nexperia.com/dam/jcr:790eaac6-e53d-4235-a3d7-4f6330fa7009/Nexperia%20Webinar%20Lost%20in%20Translation%20part%201_250522.pdf" target="_blank"&gt;https://www.nexperia.com/dam/jcr:790eaac6-e53d-4235-a3d7-4f6330fa7009/Nexperia%20Webinar%20Lost%20in%20Translation%20part%201_250522.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;For RGMII (Reduced Gigabit Media Independent Interface), the level shifters must meet specific requirements:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Low propagation delay to maintain tight timing margins (RGMII operates at 125 MHz DDR).&lt;/LI&gt;
&lt;LI&gt;Push-pull outputs (not open-drain) to support high-speed signal integrity.&lt;/LI&gt;
&lt;LI&gt;Direction-controlled or fixed-direction operation (auto-direction sensing introduces too much latency).&lt;/LI&gt;
&lt;LI&gt;Voltage translation from 3.3V to 1.8V (or vice versa, depending on PHY/SoC I/O levels).&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Device like the 74ALVC164245 from Nexperia can be a good candidate.&lt;/DIV&gt;
&lt;DIV&gt;Best regards,&lt;/DIV&gt;
&lt;DIV&gt;Pavel&lt;/DIV&gt;</description>
      <pubDate>Mon, 16 Jun 2025 10:26:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/S32K388-RGMII/m-p/2116878#M28998</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2025-06-16T10:26:51Z</dc:date>
    </item>
  </channel>
</rss>

