LS1028A: UART1 configuration

yasoua — Fri, 25 Apr 2025 10:27:27 GMT

Hello

I use scripts into TRACE32 debugger to test LS1028 peripherals (hardware tests) . I am having troubles to configure the UART1. In the reference manuel, it is mentiened that the first step is that : All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG setting in the MMU
needs to be 0b01X1.).

In the MMU, i found the I (caching enabled/ inhibited) attribute in HSCTLR and SCTLR registers, but i cannot find the other attributes (W , G, M). Could some one help me please to figure out the register containing these attributes ?

I made sure that the UART1 is enabled in RCW, and my script to configure UART1 registers and sent 1 Byte data is as below :

ENTRY &mode
LOCAL &base
&base=0x21C0000
&adresse=0x18030600

IF "&mode"=="INIT"
(

DATA.SET (&base+0x503) %BYTE 0y00000011 ; ULCR 1 UART LINE CONTROL REGISTER : no parity + 8bits word lenght + DLAB =0
DATA.SET (&base+0x501) %BYTE 0x00 ; UIER 1 UART INTERRUPT ENABLE REGISTER
DATA.SET (&base+0x502) %BYTE 0x06 ; UFCR 1 SET TO FIFO MODE : FIFO MODE DISABLED + RECEIVER AND TRANSMITTER FIFO RESET + 1 BYTE
DATA.SET (&base+0x502) %BYTE 0x01 ; UFCR 1 SET TO FIFO MODE : FIFO MODE ENABLED + RECEIVER AND TRANSMITTER FIFO NO ACTION + 1 BYTE
// DATA.SET (&base+0x502) %BYTE 0x00 ; UFCR 1 SET TO FIFO MODE : FIFO MODE DISABLED + RECEIVER AND TRANSMITTER FIFO RESET + 1 BYTE
DATA.SET (&base+0x503) %BYTE 0y1xxxxxxx ; ULCR 1 UART LINE CONTROL REGISTER : no parity + 8bits word lenght + DLAB =1
DATA.SET (&base+0x502) %BYTE 0x00 ; UAFR 1 Disable writing to each UARTn
DATA.SET (&base+0x500) %BYTE 0x05 ; UDLB 1 SET Divisor least significant byte
DATA.SET (&base+0x501) %BYTE 0x16 ; UDMB 1 SET Divisor most significant byte
// DATA.SET (&base+0x503) %BYTE 0y0xxxxxxx ; ULCR 1 UART LINE CONTROL REGISTER : no parity + 8bits word lenght + DLAB =0
)

ELSE IF "&mode"=="TX"
(

DATA.SET (&base+0x500) %BYTE 0x48 ; UART TRANSMITTER HOLDING REGISTER
WAIT 100.ms
&data1=DATA.BYTE(ANC:&base+0x500)
DATA.SET (&adresse+0x00) %BYTE &data1

DATA.SET (&base+0x500) %BYTE 0x45 ; UART TRANSMITTER HOLDING REGISTER
WAIT 100.ms
&data2=DATA.BYTE(ANC:&base+0x500)
DATA.SET (&adresse+0x01) %BYTE &data2

DATA.SET (&base+0x500) %BYTE 0x4C ; UART TRANSMITTER HOLDING REGISTER
WAIT 100.ms
&data3=DATA.BYTE(ANC:&base+0x500)
DATA.SET (&adresse+0x02) %BYTE &data3

DATA.SET (&base+0x500) %BYTE 0x4C ; UART TRANSMITTER HOLDING REGISTER
WAIT 100.ms
&data4=DATA.BYTE(ANC:&base+0x500)
DATA.SET (&adresse+0x03) %BYTE &data4

DATA.SET (&base+0x500) %BYTE 0x4F ; UART TRANSMITTER HOLDING REGISTER
WAIT 100.ms
&data5=DATA.BYTE(ANC:&base+0x500)
DATA.SET (&adresse+0x04) %BYTE &data5

PRINT %ASCII &data1 &data2 &data3 &data4 &data5

)

ENDDO

Re: LS1028A: UART1 configuration

yipingwang — Wed, 30 Apr 2025 07:35:00 GMT

Discussing with the AE team.

Re: LS1028A: UART1 configuration

yipingwang — Thu, 08 May 2025 02:50:44 GMT

All DUART registers must be mapped to a cache-inhibited and guarded area (That is, the WIMG setting in the MMU needs to be 0b01X1).
As LS1028A is based on Armv8-A architecture, memory attributes WIMG are configured using MMU's translation table.
WIMG = 0b01X1
W ( Write Through) = 0
I ( Inhibit Caching ) = 1
M (Memory coherence ) = X
G (Guarded ) = 1

which is equivalent to Device-nGnRE
cache-inhibited (I = 1)
non-gathering, non-reordering, early write ack ( G =1)
non shareable (M = x)

which can be enabled at u-boot while setup MMU in "arch/arm/cpu/armv8/fsl-layerscape/cpu.c"

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LS1028A: UART1 configuration

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