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    <title>Other NXP ProductsのトピックRe: How P3A9606JK Works</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087902#M28459</link>
    <description>&lt;P&gt;Hi Tomas,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your explanation.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have some unclear information.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1: F&lt;/SPAN&gt;or &lt;STRONG&gt;Open-drain&lt;/STRONG&gt; mode: When a port translates from high-to-low (i.e.&lt;SPAN&gt;, the master/slave driver pulls a pin low)&lt;/SPAN&gt;,&lt;SPAN&gt;&amp;nbsp;is&lt;/SPAN&gt;&amp;nbsp;there a combination both Fall Accelerator and &lt;SPAN&gt;FET pass-gate to accelerate falling edges in P3A9606JK. Or just having FET pass-gate without accelerating falling edges (i.e. falling time depend mainly on drive strength of master/slave driver)? I would like to know both&amp;nbsp;fall accelerator and rise&amp;nbsp;accelerator will not be used or just&amp;nbsp;rise&amp;nbsp;accelerator is not&amp;nbsp;used in open drain mode (rise time depends on external pull-up resistors as you explained).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q2: For &lt;STRONG&gt;Push-pull&lt;/STRONG&gt; mode: As I understand, both rise&amp;nbsp;accelerator and fall&amp;nbsp;accelerator on A and B ports are be used. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;For e.g.: When generating a transaction from A port to B port of P3A9606JK&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;+ Translate from high-to-low (device pulls low): Falling edge will be detected by Fall Accelerator at A port of P3A9606JK&amp;nbsp;and at the same time, FET pass-gate will be turned on then&amp;nbsp;Fall Accelerator at B port also detect falling edge of A side and fall time will be&amp;nbsp;accelerated by both&amp;nbsp;Fall Accelerator of A and B ports.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;+ Translate from low-to-high (device pulls high): Rising edge will&amp;nbsp;be detected by Rise Accelerator at A port of P3A9606JK and somehow (maybe there is a detector or a controller ??)&amp;nbsp;to activate&amp;nbsp;Rise Accelerator at B port. So rise&amp;nbsp;time will be&amp;nbsp;accelerated by both Rise Accelerator of A and B ports.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can you correct me if my understand is wrong?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 28 Apr 2025 03:03:28 GMT</pubDate>
    <dc:creator>vanpham</dc:creator>
    <dc:date>2025-04-28T03:03:28Z</dc:date>
    <item>
      <title>How P3A9606JK Works</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087254#M28443</link>
      <description>&lt;P&gt;Hi NXP team,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have already read the datasheet of P3A9606:&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/data-sheet/P3A9606JK.pdf" target="_self" rel="nofollow noopener noreferrer"&gt;P3A9606JK - Dual bidirectional I3C/I2C-bus and SPI voltage-level data sheet&lt;/A&gt;&lt;/P&gt;&lt;P&gt;The IC can support push pull and open drain applications. As the&amp;nbsp;13.1 Applications section, I can know how to connect Master to I2C or I3C devices.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="vanpham_0-1745577376246.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/334908i092B396F762C65D2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="vanpham_0-1745577376246.png" alt="vanpham_0-1745577376246.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I just know if the input is push-pull then the output is push-pull according to the corresponding voltage of the 2 sides (&lt;SPAN&gt;i.e. according to the example:&lt;/SPAN&gt;&amp;nbsp;the input is push-pull 1.2V then output is push-pull 1.8V) and vice versa if the input is open-drain, then the output is open drain.&lt;/P&gt;&lt;P&gt;Can you explain in detail how&amp;nbsp;P3A9606JK can work? How does the P3A9606JK know when it's push pull and when it's open drain so it can handle it properly? It has a detector, right? Based on block diagram, I cannot explain how it works properly.&lt;/P&gt;&lt;P&gt;And besides datasheet, do you have any documents about&amp;nbsp;P3A9606JK?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;LI-PRODUCT title="P3A9606JK-EVB" id="P3A9606JK-EVB"&gt;&lt;/LI-PRODUCT&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Apr 2025 10:39:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087254#M28443</guid>
      <dc:creator>vanpham</dc:creator>
      <dc:date>2025-04-25T10:39:14Z</dc:date>
    </item>
    <item>
      <title>Re: How P3A9606JK Works</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087306#M28446</link>
      <description>&lt;P&gt;Hi Van,&lt;/P&gt;
&lt;P&gt;Yes, the P3A9606JK&amp;nbsp;has detection logic, but not a "detector" block like you could see in some block diagrams. Instead, it uses a clever analog pass-gate mechanism combined with edge-rate accelerators to sense and react automatically to the type of signal being applied.&lt;/P&gt;
&lt;P&gt;The core of the P3A9606JK’s logic is an N-channel FET pass-gate between the A and B sides. This pass-gate is enabled only when the signal on one side is Low, allowing the Low signal to propagate to the other side.&amp;nbsp;When both sides are High, the pass-gate turns off, preventing any short between different supply domains.&lt;/P&gt;
&lt;P&gt;Edge-rate accelerators help with transition detection (e.g. falling edge of a push-pull signal).&amp;nbsp;They sharpen the signal edges, making it more compatible with high-speed buses like SPI and I3C.&lt;/P&gt;
&lt;P&gt;Open-drain:&amp;nbsp;Only Low is actively driven. High relies on pull-ups. The device sees the line floating and uses its internal logic to not drive the output - it just passes the Low through when detected.&lt;/P&gt;
&lt;P&gt;Push-pull:&amp;nbsp;Actively drives both High and Low. As explained before, the translator uses edge detection and pass-gates to replicate the push-pull transitions on the other side (at the translated voltage).&lt;/P&gt;
&lt;P&gt;As of now, there is no dedicated application note specifically for the P3A9606JK.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BRs, Tomas&lt;/P&gt;</description>
      <pubDate>Fri, 25 Apr 2025 12:29:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087306#M28446</guid>
      <dc:creator>TomasVaverka</dc:creator>
      <dc:date>2025-04-25T12:29:48Z</dc:date>
    </item>
    <item>
      <title>Re: How P3A9606JK Works</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087902#M28459</link>
      <description>&lt;P&gt;Hi Tomas,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your explanation.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have some unclear information.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1: F&lt;/SPAN&gt;or &lt;STRONG&gt;Open-drain&lt;/STRONG&gt; mode: When a port translates from high-to-low (i.e.&lt;SPAN&gt;, the master/slave driver pulls a pin low)&lt;/SPAN&gt;,&lt;SPAN&gt;&amp;nbsp;is&lt;/SPAN&gt;&amp;nbsp;there a combination both Fall Accelerator and &lt;SPAN&gt;FET pass-gate to accelerate falling edges in P3A9606JK. Or just having FET pass-gate without accelerating falling edges (i.e. falling time depend mainly on drive strength of master/slave driver)? I would like to know both&amp;nbsp;fall accelerator and rise&amp;nbsp;accelerator will not be used or just&amp;nbsp;rise&amp;nbsp;accelerator is not&amp;nbsp;used in open drain mode (rise time depends on external pull-up resistors as you explained).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q2: For &lt;STRONG&gt;Push-pull&lt;/STRONG&gt; mode: As I understand, both rise&amp;nbsp;accelerator and fall&amp;nbsp;accelerator on A and B ports are be used. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;For e.g.: When generating a transaction from A port to B port of P3A9606JK&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;+ Translate from high-to-low (device pulls low): Falling edge will be detected by Fall Accelerator at A port of P3A9606JK&amp;nbsp;and at the same time, FET pass-gate will be turned on then&amp;nbsp;Fall Accelerator at B port also detect falling edge of A side and fall time will be&amp;nbsp;accelerated by both&amp;nbsp;Fall Accelerator of A and B ports.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;+ Translate from low-to-high (device pulls high): Rising edge will&amp;nbsp;be detected by Rise Accelerator at A port of P3A9606JK and somehow (maybe there is a detector or a controller ??)&amp;nbsp;to activate&amp;nbsp;Rise Accelerator at B port. So rise&amp;nbsp;time will be&amp;nbsp;accelerated by both Rise Accelerator of A and B ports.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can you correct me if my understand is wrong?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 28 Apr 2025 03:03:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2087902#M28459</guid>
      <dc:creator>vanpham</dc:creator>
      <dc:date>2025-04-28T03:03:28Z</dc:date>
    </item>
    <item>
      <title>Re: How P3A9606JK Works</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2088008#M28460</link>
      <description>&lt;P&gt;Hi Van,&lt;/P&gt;
&lt;P&gt;Your understanding is correct.&amp;nbsp;In open-drain mode, the fall accelerator is used, rise accelerator not.&amp;nbsp;In push-pull mode, both fall and rise accelerators are used.&lt;/P&gt;
&lt;P&gt;BRs, Tomas&lt;/P&gt;</description>
      <pubDate>Mon, 28 Apr 2025 06:42:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2088008#M28460</guid>
      <dc:creator>TomasVaverka</dc:creator>
      <dc:date>2025-04-28T06:42:14Z</dc:date>
    </item>
    <item>
      <title>Re: How P3A9606JK Works</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2088360#M28469</link>
      <description>Hi Tomas,&lt;BR /&gt;Thank you so much.</description>
      <pubDate>Mon, 28 Apr 2025 11:36:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/How-P3A9606JK-Works/m-p/2088360#M28469</guid>
      <dc:creator>vanpham</dc:creator>
      <dc:date>2025-04-28T11:36:26Z</dc:date>
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