https://community.nxp.com/t5/Other-NXP-Products/GD3162-BIST/m-p/2061122#M27962 <P>Hi Akshat,</P> <P><SPAN>Please refer to figures 41 and 42 of the GD3162 datasheet. After setting BIST=1, INTA &amp; INTB pin will go low and BIST will be run. It can take up to 15ms for BIST to complete. When BIST is complete, INTA and INTB will go back high. The code needs to wait for this indication to read SPI. SPI read during BIST is not allowed. After BIST has completed, the code should write BIST bit to 0 and check either the state of INTA/INTB or the BIST_ERR flag to know if it was successful.</SPAN></P> <P><SPAN><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="xavier_b_0-1741855639220.png" style="width: 562px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/327918iFA7EA1564C61C5F9/image-dimensions/562x254?v=v2" width="562" height="254" role="button" title="xavier_b_0-1741855639220.png" alt="xavier_b_0-1741855639220.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">xavier_b_0-1741855639220.png</span></span></SPAN></P> <P><SPAN><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="xavier_b_1-1741855648616.png" style="width: 561px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/327921i2B6DEC2131D03292/image-dimensions/561x239?v=v2" width="561" height="239" role="button" title="xavier_b_1-1741855648616.png" alt="xavier_b_1-1741855648616.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">xavier_b_1-1741855648616.png</span></span></SPAN></P> <P><SPAN>BRs, Tomas</SPAN></P> Thu, 13 Mar 2025 08:58:43 GMT TomasVaverka 2025-03-13T08:58:43Z https://community.nxp.com/t5/Other-NXP-Products/GD3162-BIST/m-p/2060947#M27959 <P>Hi NXP,<BR />When I'm trying to perform BIST, in my project...GD is writing 3FF to all the register data bits. Why is this hapenning? Do I need to manually induce some delays before disabling BIST?<BR />I've attached the code snippet please review and let me know.</P> Thu, 13 Mar 2025 05:43:31 GMT https://community.nxp.com/t5/Other-NXP-Products/GD3162-BIST/m-p/2060947#M27959 Akshat_VE02376 2025-03-13T05:43:31Z https://community.nxp.com/t5/Other-NXP-Products/GD3162-BIST/m-p/2061122#M27962 <P>Hi Akshat,</P> <P><SPAN>Please refer to figures 41 and 42 of the GD3162 datasheet. After setting BIST=1, INTA &amp; INTB pin will go low and BIST will be run. It can take up to 15ms for BIST to complete. When BIST is complete, INTA and INTB will go back high. The code needs to wait for this indication to read SPI. SPI read during BIST is not allowed. After BIST has completed, the code should write BIST bit to 0 and check either the state of INTA/INTB or the BIST_ERR flag to know if it was successful.</SPAN></P> <P><SPAN><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="xavier_b_0-1741855639220.png" style="width: 562px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/327918iFA7EA1564C61C5F9/image-dimensions/562x254?v=v2" width="562" height="254" role="button" title="xavier_b_0-1741855639220.png" alt="xavier_b_0-1741855639220.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">xavier_b_0-1741855639220.png</span></span></SPAN></P> <P><SPAN><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="xavier_b_1-1741855648616.png" style="width: 561px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/327921i2B6DEC2131D03292/image-dimensions/561x239?v=v2" width="561" height="239" role="button" title="xavier_b_1-1741855648616.png" alt="xavier_b_1-1741855648616.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">xavier_b_1-1741855648616.png</span></span></SPAN></P> <P><SPAN>BRs, Tomas</SPAN></P> Thu, 13 Mar 2025 08:58:43 GMT https://community.nxp.com/t5/Other-NXP-Products/GD3162-BIST/m-p/2061122#M27962 TomasVaverka 2025-03-13T08:58:43Z