Other NXP ProductsのトピックGD3162 gate driver

GD3162 gate driver

Akshat_VE02376 — Mon, 27 Jan 2025 10:01:51 GMT

Can anyone clarify the requirements needed for sensing short circuit and over current faults using ISENSE pin of gate driver? In my case, when I'm trying to set a threshold voltage for OCTH and SCCOMPTH (after enabling OCSNS and SCSNS bits to 1) and even after giving a voltage greater than the threshold to the ISENSE pin , it is sporadically detecting SC fault (OC fault is not at all being detected).
I'm attaching the schematic which shows the INSENSE pin connection :

Instead of directly connecting to the MOSFET terminal, we have designed a circuit mentioned above for phase current cut off. Please explain what else is needed to get an SC and OC fault and cutoffs respectively

Re: GD3162 gate driver

TomasVaverka — Mon, 27 Jan 2025 12:48:06 GMT

Hello Anand,

Circuit connections look appropriate.

As the ISENSE/COMP is a dual purpose pin, please confirm that ISNCMP_EN bit in MODE2 register is set to 0 to activate ISENSE functionality. Also make sure that OC fault is not masked by setting the OCM bit to 1 in MSK1 register.

You mention sporadic detection of SC, no detection of OC. This could be due to the filter times on these 2 faults, filter time on OC is typically longer. Please configure using SCFF/SCFILT (100ns to 1.1µs) and OCFILT (0.5µs to 5µs) in CONFIG2 and resp. CONFIG1 registers. The positive pulse width on Isense must be much greater than these filter times to ensure reliable detection.

From your circuit, SC and OC will always be triggered simultaneously. Is there any added value in enabling both then? OC could be masked if you want to directly interrupt PWM operation...

Also, maybe the MCU/safing logic has direct access to the PH_OC_Cutoff signal? In this case, similar behavior could be achieved at lower cost (no need for optocoupler) by driving the FSENB line low (FSSTATE=0). This will turn OFF the driver using SSD as well.

BRs, Tomas

Re: GD3162 gate driver

Akshat_VE02376 — Tue, 28 Jan 2025 03:29:16 GMT

Yes, we have masked the OC fault and disabled over current fault management in the MODE2 register. We only want a PWM cut off using SSD whenever the current reaches a certain value. Yes, you are correct to figure out that the safing logic (SBC) has a direct access, but we are currently not using the failsafe state. But I still doubt that if I'm giving a constant voltage at the ISENSE pin which is greater than the threshold then how does the filter time cause the sporadic occurrence of the fault? Please clarify this, Tomas. And also is it correct to ay that DESAT_fault will always occur at times of short circuit at greater voltages?