topic in SJA1105QELY How to modify RGMII Programmable drive strength? in Other NXP Products

in SJA1105QELY How to modify RGMII Programmable drive strength?

Mehta — Fri, 24 Jan 2025 13:55:26 GMT

Dear All,

I am using SJA1105QELY Switch and i have some EMC issue with RGMII Clock (125MHz ,375 MHz 750MHZ,875MHz . i think Harmonics related peaks see attached image)

Can any one inform me the process or Register for changing the drive strength of RGMII interface . (in design 39R Series Res added may be i can try with 49 Or 50R but it would be great i can change it from some Programmable Register )

Regards,

Nikunj

Re: in SJA1105QELY How to modify RGMII Programmable drive strength?

PavelL — Mon, 27 Jan 2025 08:38:19 GMT

Hello @Mehta ,

You may decrease the drive strength. Please refer to Table 32 and Table 33 in AH1704 SJA1105PQRS Application Hints , if you use 2.5V or 3.3V RGMII, you may decrease to Medium Speed, since Fast Speed is the default - UM11040 Table 121 Software user manual for SJA1105P, SJA1105Q, SJA1105R, SJA1105S - Registers CFG_PAD_MIIx_TX / D32_OS.

You may also consider hints from AN13335, PCB Design Guidelines for Automotive Ethernet Application Note as well as check your PCB with any reference design with SJA1105, listed in Hardware section SJA1105PQRS | Automotive Ethernet Switches | NXP Semiconductors .

Best regards,

Pavel

Re: in SJA1105QELY How to modify RGMII Programmable drive strength?

Mehta — Mon, 27 Jan 2025 13:53:34 GMT

Hello Pavel,

Thank you for the informatation , i set the "Low noise / Medium Speed" . can you please infomr what exatly this mode do inside the chip ? is it related to impedance or other ? if i measure signal on CLK line it will improve compare to before default setting ?

Regarding PCB guide line and referance i alredy refer and implement my design as per suggestion .

Regards,

Nikunj

Re: in SJA1105QELY How to modify RGMII Programmable drive strength?

PavelL — Mon, 27 Jan 2025 14:18:09 GMT

Hello @Mehta ,

that is depended on used IO library IP.

I would assume that in this case, number of output transistors is chosen based on CFG_PAD_MIIx_TX / D32_OS. Higher number of transistors = faster rise/fall time on a pad = higher dV/dt = higher noise. You may refer to this picture 2.7 I/O Cells - imagine that M1 and M2 are split on several parts and you control gate for each part by a combination logic...

You should measure different rise/fall times with different driver speed.

Best regards,

Pavel

Re: in SJA1105QELY How to modify RGMII Programmable drive strength?

Mehta — Mon, 27 Jan 2025 14:34:44 GMT

Hello Pavel,
Thank you for the details , i will measure the signals and also the EMC scan and update you soon.