Other NXP ProductsのトピックFS26 FS_STATES & SPI Communication

FS26 FS_STATES & SPI Communication

pratikkul26 — Tue, 24 Dec 2024 10:45:28 GMT

We have made a circuit using MFS2613AMDA3AD.(front end) We are getting the LDO1 & LDO 2 output as 3.3V & 5V respectively. We are using the device in debug mode for initial development.

We are using SBC/PMIC -RTD version SBC FS26 R21-11 4.0.0

1)We are using the device in debug mode for initial development.
2)RSTB is not getting released.
3)When we are reading Sbc_fs26_GetDeviceState(); FS_STATES value is coming invalid(0x14h). so we are unable to proceed for Normal Sequencing as per RTD.

4)M_STATUS reg read value value is showing that VDEBUG > VDBG. & DBG_MODE bit is high(1) of FS_STATES which confirms that device is in debug mode.

5)FS_WDW_DURATION read value is matching with default settings.

What should be the SPI Mode? as per datasheet it should be Mode 3 but in example code it is configured as Mode 1. CPHA & CPOL value? Also datawidth settings can't be configured more than 8 bit as frame structure of FS26 is 32bit

Clock Speed is 5MHz.

Re: FS26 FS_STATES & SPI Communication

guoweisun — Wed, 25 Dec 2024 05:42:05 GMT

Hi pratikkul26

Could you please let me know how to enter into debug mode for SBC?

You can confirm it according below info:

Debug mode is intended for software debugging or first MCU programming during ECU assembly. To enter Debug mode without first entering OTP mode, the voltage at the DEBUG pin must be set to VDBG prior to applying the VSUP voltage. During the power-up sequence, the fail-safe state machine will start in Debug mode and reach the initialization phase

Thanks!

Re: FS26 FS_STATES & SPI Communication

pratikkul26 — Thu, 26 Dec 2024 06:55:22 GMT

Yes, we are first applying the 5V on Debug pin then giving Vsup of 12V.

Can you please confirm the SPI Mode? 1 or 3. I think we are unable to write anything to FS26.

RSTB should be released first as per state-flow given in the datasheet, then we can write to Init_FS_I Registers. then close the Init_FS by good WDG Refresh. & Release FS outputs.

Do we need to do good watchdog refresh in debug mode as well? there is no 256ms window when device is in debug mode?

Why are we getting FS_STATE = 0x14h?

Re: FS26 FS_STATES & SPI Communication

guoweisun — Thu, 26 Dec 2024 08:51:39 GMT

1: SPI timing refer to below picture:

Do we need to do good watchdog refresh in debug mode as well? there is no 256ms window when device is in debug mode?

Why are we getting FS_STATE = 0x14h?

[gw]You need do good WD to close INIT phase,and refresh WD to decrease fault error counter circled below.