topic VR5510 Reading FS Register in Other NXP Products

VR5510 Reading FS Register

tjdwonB — Sat, 03 Aug 2024 08:43:09 GMT

Hello.

I am reading the FS register via VR5510 I2C, and I have a question because there is something strange.

1. The FS_OVUVREG_STATUS register responds as 55 54 89,

which is interpreted as VCOREMON UV, VDDIO UV, VMON1~4 UV, HVLDOMON UV.

However, when I actually measure the monitoring node with an oscilloscope, it is in normal operation. (Photo attached)

2. When I check the datasheet, it says that the FS Register and FS_NOT Register should be read in a complement relationship.

However, in the case of 0x07h and 0x08h, 0x0B and 0x0C, some data are not read in complement.

0x07 is WD_RFR_CNT(000b <-> 000b) and WD_ERR_CNT(0000b <-> 0000b) values,

0x0B is FLT_ERR_CNT(0110b <-> 0000b) value, and it responds like the data in the parentheses.

3. In the data read from FS_DIAG_SAFETY(REGADD 0x16), there seems to be no problem with I2C, but the I2C_FS_REQ value is responding as 1(I2C Violation).

I would like to ask for help on what the suspected cause is and how to resolve it.

Re: VR5510 Reading FS Register

tjdwonB — Sat, 03 Aug 2024 08:50:55 GMT

As additional information, the Main register has never been read or written.

And because of the content of the original post, I doubt that all the FS register data currently being responded to are correct values.

Re: VR5510 Reading FS Register

TomasVaverka — Wed, 07 Aug 2024 07:18:09 GMT

Hello Sung-Won,

1. After each power-up or wake up from PWRON pin, the VR5510 executes the regulator power-up sequence and after that, software driver should clear all the flags by writing in FS_DIAG_SAFETY, FS_OVUVREG_STATUS.

The UV faults you read are faults reported during power up sequence, but not the real UV reported after power up.

Please check chapter 8 - Start-up sequence in VR5510 Safety Manual.

2. Only the write bits have their complement register bits in FS_I_NOT. The WD_RFR_CNT, WD_ERR_CNT, FLT_ERR_CNT register bits are read only , so their corresponding bits are reserved (all 0).

3. Please check A1, after each power-up or wake up from PWRON pin software driver should clear all the flags by writing all bit '1' in FS_DIAG_SAFETY.

BRs, Tomas

Re: VR5510 Reading FS Register

tjdwonB — Thu, 08 Aug 2024 08:19:37 GMT

Thank you for the reply.

1. First of all, I can't found VR5510 Safety manual. Is it different with document named AN13118?

2. I can't find any information in the VR5510 data sheet that the register I mentioned earlier is read only.I can't find any information in the VR5510 data sheet that the register I mentioned earlier is read only. (datasheet Rev. 6 / page 132)

The VR5510 datasheet states that it is capable of both read and write. If the VR5510 Safety Manual you provided says read only, it seems like the information is different from the datasheet. However, if read only is the correct information, this problem probably doesn't need to worry anymore.

3. I'll try it. Is this information also in the VR5510 Safety Manual?

Best regards, sungwon

Re: VR5510 Reading FS Register

TomasVaverka — Thu, 08 Aug 2024 13:01:06 GMT

Hello Sung-Won,

1. Yes, it is different. The VR5510 Safety Manual is classified as a secure file (requiring an NDA) and can be downloaded from:
https://www.nxp.com/products/power-management/pmics-and-sbcs/pmics/multi-channel-9-pmic-for-s32g-processor-8-high-power-1-low-power-fit-for-asil-d-safety-level:VR5510

For more information about accessing the authorized secure information, please visit:
https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS

2. Unfortunately the datasheet is incorrect in this regard, the WD_RFR_CNT, WD_ERR_CNT, FLT_ERR_CNT register bits are indeed read only. I will ask the responsible team for correction.

3. Yes.

BRs, Tomas

Re: VR5510 Reading FS Register

tjdwonB — Fri, 09 Aug 2024 11:58:00 GMT

It's really frustrate to hear that the "VR5510 Safety Manual" requires an NDA.

Please check if I understood the "VR5510 Safety Manual chapter 8 - Start-up sequence" image correctly what you attached.

1. In item 4, does "clear the fault error counter to 0" mean to write FLT_ERR_CNT of FS_I_FSSM register to 0?

2. I don't quite understand the meaning of "perform 'RSTB/FS0B' path check". Does it mean the circuit path or to check the node to release RSTB/FS0B?

3. After the power up sequence is finished, if I perform steps 3 and 4 and release RSTB, should I perform steps 3 and 4 again?

4. Does releasing RSTB and FS0B mean that RSTB and FS0B are asserted? If so, is RSTB asserted low after performing step 4 and FS0B asserted after performing step 5?

5. The VR5510 I'm using has an OTP ID of DAH and WD is disabled. Do I still need to perform step 8?

6. If I don't need to perform step 8, can I check FS_GRL_FLAGS after step 7?

Best regards, sungwon