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    <title>topic Re: sja1105s in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923906#M24662</link>
    <description>&lt;P&gt;As shown in the block diagram, SOC1 SOC2 and MCU chips are connected to the switch by RGMII interface. SOC1 and SOC2 run the linux operating system, and MCU run the real-time OS. The switch driver is on the SOC1. SOC1 configure the switch(sja1105s)'s registers through spi interface. When the ECU is powered on, MCU initializes in a very short time, the SOC1 and SOC2 take about 10 seconds to up. The start time of SOC1 and SOC2 are the same.&lt;/P&gt;&lt;P&gt;First, the switch driver and mac driver are compiled into the linux kernel,sometimes the network is normal and SOC1 can ping to SOC2. Sometimes, the network is unnormal and SOC1 can't ping to SOC2. Later, the switch driver is compiled to the form ".ko".When load the switch driver by using “insmod” after SOC1 and SOC2 all uped, the network always worked and SOC1 can always ping to SOC2. Recently, there is a problem that the mac is reinitialized by system, and afer reinitialize SOC1 can not ping to SOC2 until rmmod switch drvier and insmod switch driver.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="IMG_20240802_180926.jpg" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291683i3555A25CBB89F5FC/image-size/large?v=v2&amp;amp;px=999" role="button" title="IMG_20240802_180926.jpg" alt="IMG_20240802_180926.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 02 Aug 2024 10:13:36 GMT</pubDate>
    <dc:creator>qixue</dc:creator>
    <dc:date>2024-08-02T10:13:36Z</dc:date>
    <item>
      <title>sja1105s</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923669#M24653</link>
      <description>&lt;P&gt;Hi，I'm using the sja1105s switch chips. The current situation is that two SOC chips and one MCU chip are connected to this chip. The mac drivers of three chips must be loaded first and switch driver is loaded after, then the network will work normally. If load the switch chip driver before the mac drivers, the network will not work. The SOC can not ping to each other. So i want to know if it is normal for the switch driver must be loaded before mac driver or i configured some import registers of switch?&lt;/P&gt;&lt;P&gt;Thank you in advance,&lt;/P&gt;&lt;P&gt;Let me know if you need anymore information from me.&lt;/P&gt;</description>
      <pubDate>Fri, 02 Aug 2024 05:55:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923669#M24653</guid>
      <dc:creator>qixue</dc:creator>
      <dc:date>2024-08-02T05:55:24Z</dc:date>
    </item>
    <item>
      <title>Re: sja1105s</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923743#M24655</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;please, can you share a simple block diagram where all devices (incl. part numbers) and their connectivity (with bus names) will be well seen?&lt;/P&gt;
&lt;P&gt;It would be also helpful if you can somehow mark the wrong &amp;amp; right order of driver's load.&lt;/P&gt;
&lt;P&gt;Thank you.&amp;nbsp;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Fri, 02 Aug 2024 07:14:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923743#M24655</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-08-02T07:14:57Z</dc:date>
    </item>
    <item>
      <title>Re: sja1105s</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923906#M24662</link>
      <description>&lt;P&gt;As shown in the block diagram, SOC1 SOC2 and MCU chips are connected to the switch by RGMII interface. SOC1 and SOC2 run the linux operating system, and MCU run the real-time OS. The switch driver is on the SOC1. SOC1 configure the switch(sja1105s)'s registers through spi interface. When the ECU is powered on, MCU initializes in a very short time, the SOC1 and SOC2 take about 10 seconds to up. The start time of SOC1 and SOC2 are the same.&lt;/P&gt;&lt;P&gt;First, the switch driver and mac driver are compiled into the linux kernel,sometimes the network is normal and SOC1 can ping to SOC2. Sometimes, the network is unnormal and SOC1 can't ping to SOC2. Later, the switch driver is compiled to the form ".ko".When load the switch driver by using “insmod” after SOC1 and SOC2 all uped, the network always worked and SOC1 can always ping to SOC2. Recently, there is a problem that the mac is reinitialized by system, and afer reinitialize SOC1 can not ping to SOC2 until rmmod switch drvier and insmod switch driver.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="IMG_20240802_180926.jpg" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291683i3555A25CBB89F5FC/image-size/large?v=v2&amp;amp;px=999" role="button" title="IMG_20240802_180926.jpg" alt="IMG_20240802_180926.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Aug 2024 10:13:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1923906#M24662</guid>
      <dc:creator>qixue</dc:creator>
      <dc:date>2024-08-02T10:13:36Z</dc:date>
    </item>
    <item>
      <title>Re: sja1105s</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1978831#M26007</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238123"&gt;@qixue&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;I apologize for the delay.&lt;/P&gt;
&lt;P&gt;It sounds similar to RGMII tunable line erratum described in 6.1.13.3 Frequency Transitions of AH1704. The SW config has nothing to do here. As far as I understand the application hints, the workaround is outside the sja1105 driver. The workaround then would be to see if it's possible to pause the RGMII clock of the SOC2 MAC for the required duration as specified in AH1704.&lt;BR /&gt;Let me know if this workaround is not possible then we can think about other options.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Tue, 22 Oct 2024 06:18:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1978831#M26007</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-22T06:18:27Z</dc:date>
    </item>
    <item>
      <title>Re: sja1105s</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1982028#M26079</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238123"&gt;@qixue&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;can you share at which speed you use the RGMII port?&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Fri, 25 Oct 2024 12:13:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/sja1105s/m-p/1982028#M26079</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-25T12:13:04Z</dc:date>
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