Re: CPU not Halted when jlink segger debug is used on Module : PN7642

Ketul — Wed, 20 Dec 2023 07:19:06 GMT

Hi All ,

I am not able to flash my hex file in to PN7642 using J Link segger , when try to flash I am geting error like CPU not halted , please find below log:

IDE : MCU EXPRESSO IDE VERSION 11.8

Jlink segger version : V7.92

SEGGER J-Link Commander V7.92l (Compiled Oct 25 2023 15:22:50)

DLL version V7.92l, compiled Oct 25 2023 15:21:06

J-Link Command File read successfully.

Processing script file...

J-Link>ExitOnError 1

J-Link Commander will now exit on Error

J-Link :r

J-Link connection not established yet but required for command.

Connecting to J-Link via USB...O.K.

Firmware: J-Link V9 compiled May 7 2021 16:26:12

Hardware version: V9.30

J-Link uptime (since boot): N/A (Not supported by this model)

S/N: 609300836

License(s): RDI, FlashBP, FlashDL, JFlash, GDB

VTref=3.282V

Target connection not established yet but required for command.

Device "PN7642" selected.

Connecting to target via SWD

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

Scanning AP map to find all available APs

AP[1]: Stopped AP scan as end of AP map seems to be reached

AP[0]: AHB-AP (IDR: 0x84770001)

Iterating through AP map to find AHB-AP to use

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

Cortex-M (ARMv8-M and later): The connected J-Link (S/N 609300836) uses an old firmware module that does not handle I/D-cache correctly. Proper debugging functionality cannot be guaranteed if cache is enabled

FPUnit: 8 code (BP) slots and 0 literal slots

Security extension: implemented

Secure debug: disabled

CoreSight components:

ROMTbl[0] @ E00FE000

[0][0]: E00FF000 CID B105100D PID 000BB4C9 ROM Table

ROMTbl[1] @ E00FF000

[1][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33

[1][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT

[1][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB

[1][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM

[1][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM

[1][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI

[0][1]: E0045000 CID B105900D PID 004BB907 DEVARCH 00000000 DEVTYPE 21 ETB

[0][2]: E0045000 CID B105900D PID 004BB907 DEVARCH 00000000 DEVTYPE 21 ETB

[0][3]: E0044000 CID B105900D PID 002BB909 DEVARCH 00000000 DEVTYPE 22 ATBR (?)

[0][4]: E0046000 CID B105900D PID 005BB906 DEVARCH 00000000 DEVTYPE 14 CTI (?)

Memory zones:

"Default" Description: Default access mode

Cortex-M33 identified.

Reset delay: 0 ms

Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: Core did not halt after reset, trying to disable WDT.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: CPU did not halt after reset.

Reset: Using fallback: Reset pin.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Core did not halt after reset, trying to disable WDT.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Failed. Toggling reset pin and trying reset strategy again.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: Core did not halt after reset, trying to disable WDT.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: CPU did not halt after reset.

Reset: Using fallback: Reset pin.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Core did not halt after reset, trying to disable WDT.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

****** Error: Failed to halt CPU.

J-Link>h

CPU could not be halted

J-Link>loadfile "C:\Users\40024076\Documents\MCUXpressoIDE_11.8.1_1197\workspace\pnev7642fama_NfcrdlibEx9_NTagI2C_Bm_Pub\Debug\pnev7642fama_NfcrdlibEx9_NTagI2C_Bm_Pub.hex"

'loadfile': Performing implicit reset & halt of MCU.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: Core did not halt after reset, trying to disable WDT.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: CPU did not halt after reset.

Reset: Using fallback: Reset pin.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Core did not halt after reset, trying to disable WDT.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Failed. Toggling reset pin and trying reset strategy again.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: Core did not halt after reset, trying to disable WDT.

Reset: ARMv8M core with Security Extension enabled detected.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Core did not halt after reset, halting it manually.

Reset: CPU did not halt after reset.

Reset: Using fallback: Reset pin.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

Reset: Core did not halt after reset, trying to disable WDT.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via reset pin

Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).

Reset: Reconnecting and manually halting CPU.

Found SW-DP with ID 0x6BA02477

DPIDR: 0x6BA02477

CoreSight SoC-400 or earlier

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[0]: Core found

AP[0]: AHB-AP ROM base: 0xE00FE000

CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)

Feature set: Mainline

Cache: No cache

Found Cortex-M33 r0p4, Little endian.

CPU could not be halted

****** Error: Failed to halt CPU.

CPU could not be halted

Downloading file [C:\Users\40024076\Documents\MCUXpressoIDE_11.8.1_1197\workspace\pnev7642fama_NfcrdlibEx9_NTagI2C_Bm_Pub\Debug\pnev7642fama_NfcrdlibEx9_NTagI2C_Bm_Pub.hex]...

topic Re: CPU not Halted when jlink segger debug is used on Module : PN7642 in Other NXP Products

CPU not Halted when jlink segger debug is used on Module : PN7642

Re: CPU not Halted when jlink segger debug is used on Module : PN7642

Re: CPU not Halted when jlink segger debug is used on Module : PN7642

Re: CPU not Halted when jlink segger debug is used on Module : PN7642