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    <title>Other NXP ProductsのトピックRe: Questions regarding T2081(T4240) PCI Express driver code.</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/Questions-regarding-T2081-T4240-PCI-Express-driver-code/m-p/1814571#M21327</link>
    <description>&lt;P&gt;&lt;SPAN&gt;a) The QorIQ T4 family of processors offers the highest performance for networking application and is commonly used as a PCI host.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;b) For OpenHostOutWindow(), suggest customer refer to the MM_Init() function and two invocations as below in order to futher understand the memory manage intent.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Initialize a memory manage object to manage PCI virtual memory space for this bus*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;retVal = MM_Init(&amp;amp;p_PciBus-&amp;gt;h_PciVirtMemMng, PCI_VIRT_SPACE_BASE, PCI_VIRT_SPACE_SIZE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Create MM object for the all pci memory space */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;rc = MM_Init(&amp;amp;(p_PciCtrl-&amp;gt;h_PciOutboundMem),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; XX_VirtToPhys((void*)p_PciCtrl-&amp;gt;localAccessWindowBase),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; p_PciCtrl-&amp;gt;localAccessWindowSize);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;c) For OpenHostInWindow(), the base address depends on the partitionId(e_MEM_1ST_DDR_NON_CACHEABLE) as below,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; p_DevDriverData-&amp;gt;p_InTransAddr[0] = (uint8_t *)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; XX_MallocSmart(size, e_MEM_1ST_DDR_NON_CACHEABLE, size); /* 16M DDR */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Master memory partitions */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#ifdef NCSW_64_BIT_ARCH&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define MEMORY_INFO \&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{ /* Region ID Memory partition ID Phys. Addr. Virt. Addr. Size */\&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {e_PLATFORM_MEM_RGN_DDR1, e_MEM_1ST_DDR_CACHEABLE, 0x00000000, 0x00000000, (1 * GIGABYTE) },\&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {e_PLATFORM_MEM_RGN_DDR1, e_MEM_1ST_DDR_NON_CACHEABLE, 0x40000000, 0x40000000, (512 * MEGABYTE) },\&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 23 Feb 2024 10:33:12 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2024-02-23T10:33:12Z</dc:date>
    <item>
      <title>Questions regarding T2081(T4240) PCI Express driver code.</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Questions-regarding-T2081-T4240-PCI-Express-driver-code/m-p/1811492#M21215</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am looking for the T2081 based PCI-Express driver code. I got the equivalent T4240 PCI express driver code from the link shared by NXP:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/qoriq-communication-processors/p-series/netcomm-software-resources:NetComm_Software?_gl=1*edodv1*_ga*MTk0NTgyNTE0OS4xNzA4NDA4NzUx*_ga_WM5LE0KMSH*MTcwODQwODc1MC4xLjAuMTcwODQwODc1MC4wLjAuMA." target="_blank"&gt;https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/qoriq-communication-processors/p-series/netcomm-software-resources:NetComm_Software?_gl=1*edodv1*_ga*MTk0NTgyNTE0OS4xNzA4NDA4NzUx*_ga_WM5LE0KMSH*MTcwODQwODc1MC4xLjAuMTcwODQwODc1MC4wLjAuMA.&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a few questions regarding the same:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;With respect to the PCI-Express module in the code, &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-There is an End point agent for 8569(Init8569AgentDeviceForDdr3() )&amp;nbsp; and for 1023(Init1023AgentDevice() ), but there is no agent for T4240. Is there a reason for that? &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-For the function&amp;nbsp;OpenHostOutWindow(), the base address is got by MM_GET() which, it seems, gets the memory allocated from the heap and then gets a Virtual address assigned to this allocated address. Also the translation address is also got by MM_GET(). Is there a logical reason for this? Should not the translation address be pointing to the actual PCI device address? &amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-Also, For the OpenHostInWindow, the translation address is got by MallocSmart() which allocates memory in the T4240 RAM DDR_NON_CACHEABE space and the base address is got by MM_GET(). In this case I understand that the translation address should point to the internal host memory space but where should the base address be pointing to? &amp;nbsp; Can you please clarify the above? Thanks very much for the same.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;thanks and regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Rajkumar&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 20 Feb 2024 06:10:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Questions-regarding-T2081-T4240-PCI-Express-driver-code/m-p/1811492#M21215</guid>
      <dc:creator>rajvad</dc:creator>
      <dc:date>2024-02-20T06:10:05Z</dc:date>
    </item>
    <item>
      <title>Re: Questions regarding T2081(T4240) PCI Express driver code.</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Questions-regarding-T2081-T4240-PCI-Express-driver-code/m-p/1814571#M21327</link>
      <description>&lt;P&gt;&lt;SPAN&gt;a) The QorIQ T4 family of processors offers the highest performance for networking application and is commonly used as a PCI host.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;b) For OpenHostOutWindow(), suggest customer refer to the MM_Init() function and two invocations as below in order to futher understand the memory manage intent.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Initialize a memory manage object to manage PCI virtual memory space for this bus*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;retVal = MM_Init(&amp;amp;p_PciBus-&amp;gt;h_PciVirtMemMng, PCI_VIRT_SPACE_BASE, PCI_VIRT_SPACE_SIZE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Create MM object for the all pci memory space */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;rc = MM_Init(&amp;amp;(p_PciCtrl-&amp;gt;h_PciOutboundMem),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; XX_VirtToPhys((void*)p_PciCtrl-&amp;gt;localAccessWindowBase),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; p_PciCtrl-&amp;gt;localAccessWindowSize);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;c) For OpenHostInWindow(), the base address depends on the partitionId(e_MEM_1ST_DDR_NON_CACHEABLE) as below,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; p_DevDriverData-&amp;gt;p_InTransAddr[0] = (uint8_t *)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; XX_MallocSmart(size, e_MEM_1ST_DDR_NON_CACHEABLE, size); /* 16M DDR */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Master memory partitions */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#ifdef NCSW_64_BIT_ARCH&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#define MEMORY_INFO \&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{ /* Region ID Memory partition ID Phys. Addr. Virt. Addr. Size */\&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {e_PLATFORM_MEM_RGN_DDR1, e_MEM_1ST_DDR_CACHEABLE, 0x00000000, 0x00000000, (1 * GIGABYTE) },\&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {e_PLATFORM_MEM_RGN_DDR1, e_MEM_1ST_DDR_NON_CACHEABLE, 0x40000000, 0x40000000, (512 * MEGABYTE) },\&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 23 Feb 2024 10:33:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Questions-regarding-T2081-T4240-PCI-Express-driver-code/m-p/1814571#M21327</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-02-23T10:33:12Z</dc:date>
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