Other NXP ProductsのトピックRe: LPC4078 Disable ISP or delay bootup ISP recognition

LPC4078 Disable ISP or delay bootup ISP recognition

ryan_jacky — Wed, 07 Feb 2024 10:04:43 GMT

Hey experts,

unfortunately we connected in our product pin P2[10] of LPC4078 to a signal which can be LOW at startup for appr. 10ms which starts ISP programming mode what I checked with debugger and a oscilloscope.

As described in datasheet after startup when VCC is present and a rising-edge on RESET occurs (=general startup), pin P2[10] is sampled for 3ms and then it decides whether starting ISP programming mode or starting user code.

How can I avoid this behavior?

Since we want to avoid a pcb redesign we're searching for a software solution.

In datasheet I read for CRP3:

This is similar to CRP2, but ISP entry by pulling P2[10] LOW is disabled if a valid user code
is present in flash sector 0.
This mode effectively disables ISP override using the P2[10] pin. It is up to the user’s
application to provide for flash updates by using IAP calls or by invoking ISP with UART0.

Until now we only use CRP2 because we want to be able to erase flash by SWD and re-flash a completely new program.

I know what "invoking ISP" with IAP calls means but it's written with "or". Is there a difference of "IAP calls" and "invoking ISP"? (For me it's the same and belongs together)

IAP calls are very uncomfortable and we don't want to use it.

Is there another possibility to disable ISP at startup?

In the following flowchart there is a decision "Watchdog Flag Set?" What does "yes - flag set" mean and how does it work? Is there a possibility to bypass "Enter ISP Mode?" with this Watchdog Flag Set?

ryan_jacky_2-1707299424934.png

Or does "Watchdog Flag Set" mean that a watchdog reset occured and because after restart it's not a normal restart the system directly executes user code to handle and evaluate the WD occurance and there's no need for ISP because ISP is only needed on regular POR startups?

I found this graphic:

ryan_jacky_3-1707299838702.png

Would there be another possibility, e.g. to delay complete startup process for some milliseconds so that our external signal on P2[10] is high and ISP won't start?

Or are there some "fuse bits" available as on Microchip µC to disable specific features (like ISP-feature)?

What would you suggest?

Thanks in advance for some hints and proposals.

Re: LPC4078 Disable ISP or delay bootup ISP recognition

xiangjun_rong — Tue, 20 Feb 2024 03:32:02 GMT

Hi,

Unfortunately, the LPC4078 does not have OTP module, you can not configure OTP to control the boot process.

As you know that the P2[10] pin must be high logic during/after Reset if you want to execute application in flash.

Because of mistake, you can not make the P2[10] high during/after Reset, I have not solution to avoid sampling P2[10] pin during/after Reset.

Using CRP3 can disable sample P2[10], but maybe there is drawback if you want to use JTAG to reprogram the chip.

XiangJun Rong

Re: LPC4078 Disable ISP or delay bootup ISP recognition

ryan_jacky — Tue, 20 Feb 2024 07:18:14 GMT

Hi XiangJun,

OTP has drawbacks, too, therefore this isn't important.

It's a pity that there's no other solution like "fuse bits" in other mirocontrollers.

We've got 3 solutions:

Strong pullup to prevent P2[10] during startup but this has further disadvantages.
Syncronized startup of P2[10] with Reset, but that's quite marginal (3ms sampling...)
Change our PCB layout and connect the line instead of P2[10] to another one. This is obviously most work but the safest solution. We prefer this one.

BR,

Daniel