https://community.nxp.com/t5/Other-NXP-Products/Can-the-SPT-trigger-FastDMA/m-p/1795046#M20899 <P>The evt command can already trigger the CPU to start Fast DMA which send RFFT result data from SRAM to DDR, but the second half of the DDR data is incorrect.</P><P>I have the following two questions that need help. Could someone please help me? Thank you.<BR /><BR />1.Does the SPT RFFT need to complete processing an entire frame of data before starting Fast DMA？<BR />2.Can I start Fast DMA when SPT RFFT processing only half of the frame? How can I starting FDMA to send data when the RFFT has processed half of the frame?</P> Thu, 25 Jan 2024 03:07:42 GMT CelineChan 2024-01-25T03:07:42Z https://community.nxp.com/t5/Other-NXP-Products/Can-the-SPT-trigger-FastDMA/m-p/1794202#M20872 <P>HW:S32R45+tef82xx</P><P>RSDK1.1.0</P><P>bsp33</P><P>&nbsp;</P><P><STRONG>Can the SPT trigger FastDMA once when the SPT RFFT processes 1/2 frame, and then trigger FastDMA again when the entire frame RFFT is complete?&nbsp;</STRONG></P><P><STRONG><SPAN>Will the ADC data in the chirp buffer be lost or overwritten between the SPT evt and wait commands?&nbsp;</SPAN>thank you.</STRONG></P><P><STRONG><SPAN>As a supplement,&nbsp;</SPAN><SPAN>When TEF82xx sends two chirps data, it will trigger the SPT to start&nbsp; RFFT without waiting for all FMCW chirps to be sent over.</SPAN></STRONG></P><P>&nbsp;</P><P>like this:</P><P>/*=========================================================================<BR />* LOOP: loop count 2 as SDADC sample array is double buffered, array holds samples of two chirps<BR />*=========================================================================*/<BR />loop #2</P><P>/*=========================================================================<BR />* LOOP: loop count is chirp number per frame divided by two as samples of two chirps are buffered<BR />*=========================================================================*/<BR />loop #(CHIRPS_PER_FRAME &gt;&gt; 2)</P><P>/*=========================================================================<BR />* LOOP: loop count 2 as SDADC sample array is double buffered, array holds samples of two chirps<BR />*=========================================================================*/<BR />loop #2</P><P>/*=========================================================================<BR />* START of THREAD SCS0<BR />*=========================================================================*/<BR />thread .thd_scs0</P><P>/*=========================================================================<BR />* PDMA: transfer SDADC samples from even/odd chirp of all channels(CH#0..CH#7) from CBRAM/SRAM to OPRAM<BR />*=========================================================================*/<BR />pdma.ind .signext .16real .sysram2opram .sync .notrace .nocoherent, SAMPLES_PER_CHIRP, RSDK_SPT_RANGE_INPUT_BASE_ADDR, WR_11, 0x0, 0x1, 0x0, 0x8<BR />pdma.ind .signext .16real .sysram2opram .sync .notrace .nocoherent, SAMPLES_PER_CHIRP, RSDK_SPT_RANGE_INPUT_BASE_ADDR, WR_12, 0x0, 0x1, 0x0, 0x8</P><P>......<BR />......</P><P><BR />/*=========================================================================<BR />* STOP of THREAD SCS0<BR />*=========================================================================*/<BR />stop</P><P>&nbsp;</P><P>/*=========================================================================<BR />* NEXT: end of inner loop<BR />*=========================================================================*/<BR />next</P><P>&nbsp; &nbsp;<BR />/*=========================================================================<BR />* NEXT: end of outer loop<BR />*=========================================================================*/<BR />next</P><P>/*=========================================================================<BR />* EVT: set event-0x1f<BR />*=========================================================================*/<BR /><STRONG>evt.cpu 0x1F</STRONG><BR />&nbsp; &nbsp;&nbsp;<BR />/*=========================================================================<BR />* WAIT: wait for SW generated event<BR />*=========================================================================*/<BR /><STRONG>wait.cpu 0x1F</STRONG></P><P><BR />/*=========================================================================<BR />&nbsp;* NEXT: end of inner loop<BR />&nbsp;*=========================================================================*/<BR />&nbsp;next</P> Wed, 24 Jan 2024 06:11:12 GMT https://community.nxp.com/t5/Other-NXP-Products/Can-the-SPT-trigger-FastDMA/m-p/1794202#M20872 CelineChan 2024-01-24T06:11:12Z https://community.nxp.com/t5/Other-NXP-Products/Can-the-SPT-trigger-FastDMA/m-p/1795046#M20899 <P>The evt command can already trigger the CPU to start Fast DMA which send RFFT result data from SRAM to DDR, but the second half of the DDR data is incorrect.</P><P>I have the following two questions that need help. Could someone please help me? Thank you.<BR /><BR />1.Does the SPT RFFT need to complete processing an entire frame of data before starting Fast DMA？<BR />2.Can I start Fast DMA when SPT RFFT processing only half of the frame? How can I starting FDMA to send data when the RFFT has processed half of the frame?</P> Thu, 25 Jan 2024 03:07:42 GMT https://community.nxp.com/t5/Other-NXP-Products/Can-the-SPT-trigger-FastDMA/m-p/1795046#M20899 CelineChan 2024-01-25T03:07:42Z