<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Other NXP ProductsのトピックSPT3.1 OPRAM about pdma command bank</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/SPT3-1-OPRAM-about-pdma-command-bank/m-p/1740995#M19690</link>
    <description>&lt;P&gt;pdma command direct control SE (banks 8-11) and&amp;nbsp;NE (banks12–15).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Shi_test_0-1697524180787.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/245442iF589D013C24B0329/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Shi_test_0-1697524180787.png" alt="Shi_test_0-1697524180787.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Shi_test_0-1697524180787.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;↑↑↑↑↑↑↑↑↑↑↑↑↑S32R45 Reference Manual ——Table 629.↑↑↑↑↑↑↑↑↑↑↑&lt;/P&gt;&lt;P&gt;So if i have a pdma command in SCS0 or MCS,the SE and NE all will get pdma data.&lt;/P&gt;&lt;P&gt;Do I understand it correctly?&lt;/P&gt;</description>
    <pubDate>Tue, 17 Oct 2023 06:30:58 GMT</pubDate>
    <dc:creator>Shi_test</dc:creator>
    <dc:date>2023-10-17T06:30:58Z</dc:date>
    <item>
      <title>SPT3.1 OPRAM about pdma command bank</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SPT3-1-OPRAM-about-pdma-command-bank/m-p/1740995#M19690</link>
      <description>&lt;P&gt;pdma command direct control SE (banks 8-11) and&amp;nbsp;NE (banks12–15).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Shi_test_0-1697524180787.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/245442iF589D013C24B0329/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Shi_test_0-1697524180787.png" alt="Shi_test_0-1697524180787.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Shi_test_0-1697524180787.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;↑↑↑↑↑↑↑↑↑↑↑↑↑S32R45 Reference Manual ——Table 629.↑↑↑↑↑↑↑↑↑↑↑&lt;/P&gt;&lt;P&gt;So if i have a pdma command in SCS0 or MCS,the SE and NE all will get pdma data.&lt;/P&gt;&lt;P&gt;Do I understand it correctly?&lt;/P&gt;</description>
      <pubDate>Tue, 17 Oct 2023 06:30:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SPT3-1-OPRAM-about-pdma-command-bank/m-p/1740995#M19690</guid>
      <dc:creator>Shi_test</dc:creator>
      <dc:date>2023-10-17T06:30:58Z</dc:date>
    </item>
    <item>
      <title>Re: SPT3.1 OPRAM about pdma command bank</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SPT3-1-OPRAM-about-pdma-command-bank/m-p/1741988#M19710</link>
      <description>&lt;P&gt;Hi Shi_test,&lt;/P&gt;&lt;P&gt;The PDMA module/accelerator is directly connected to SE and NE OPRAM controllers, meaning that it has lowest-latency access to the OPRAM banks managed by these controllers. However the PDMA can still access (read/write) the other OPRAM banks via the SW and NW controllers but such an access must be forwarded to those controllers meaning it has higher latency.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Gary&lt;/P&gt;</description>
      <pubDate>Wed, 18 Oct 2023 09:03:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SPT3-1-OPRAM-about-pdma-command-bank/m-p/1741988#M19710</guid>
      <dc:creator>GaryRK</dc:creator>
      <dc:date>2023-10-18T09:03:07Z</dc:date>
    </item>
  </channel>
</rss>

