Other NXP Products中的主题 Re: LS1027A PORESET

LS1027A PORESET

JOM_alor — Fri, 07 Jul 2023 06:43:07 GMT

Hi,

I am designing a CPU based on the LS1027A. In the reference manual LS1028ARM (Table 12) is defined the power-on sequence for that device. The question is related with the initial stages and PORESET.

Is it necessary to perform a full PORESET pulse (falling and rising edge) or is it enought to mantain PORESET low more than 1ms after all power rails are ok and then rise it to '1'?

If the second option is possible it is easy to do that with a voltage monitor.

Thanks in advance.

Re: LS1027A PORESET

mrudangshelat-13 — Fri, 07 Jul 2023 09:31:15 GMT

Hi @JOM_alor,

The PORESET_B signal should be asserted for atleast 1ms after all the supply rails are stable.

Regards,
Mrudang

Re: LS1027A PORESET

JOM_alor — Fri, 07 Jul 2023 09:40:23 GMT

Hi,

OK. But the question is: should I assert PORESET_B with a "full" assertion pulse (1 ==> 0 ==> 1) or can I mantain PORESET_B al low level from power-supply startup and after at least 1ms deasset it (0 ==> 1)?

Many thanks for your fast answer!

Re: LS1027A PORESET

mrudangshelat-13 — Mon, 10 Jul 2023 05:11:02 GMT

Hi @JOM_alor,

The PORESET_B signal must be low till the all the supplies are stable which means there will be 0==>1 logic.

Regards,
Mrudang