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    <title>Other NXP Products中的主题 Re: Dual RISC processor in MSC8156</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196767#M1828</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Based on the 8156 RM, both MAPLE-B and QUICC Engine have Dual RISC Engine. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In 8156 PB, on page 11, it says &amp;nbsp;&lt;/P&gt;&lt;P&gt;The QUICC Engine subsystem includes dual RISC processors and 48-Kbyte multi-master RAM&lt;BR /&gt;to handle the Ethernet and SPI interfaces, thus off loading the tasks from the cores. The three&lt;BR /&gt;communication controllers support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 01 May 2010 02:48:03 GMT</pubDate>
    <dc:creator>starcoreDSP</dc:creator>
    <dc:date>2010-05-01T02:48:03Z</dc:date>
    <item>
      <title>Dual RISC processor in MSC8156</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196766#M1827</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;The MSC8156 Block Diagram in document "MSC8156 Product Brief" show that MAPLE-B has a Dual RISC Engine, but the block Diagram in document "MSC8156 Data Sheet" show that there is no Dual RISC Engine in MAPLE-B and there are Dual RISC Processors in QUICC Engine Subsystem. &lt;/P&gt;&lt;P&gt;I want to ask whether both of their have Dual RISC processor. Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Apr 2010 10:36:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196766#M1827</guid>
      <dc:creator>lpeng</dc:creator>
      <dc:date>2010-04-30T10:36:07Z</dc:date>
    </item>
    <item>
      <title>Re: Dual RISC processor in MSC8156</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196767#M1828</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Based on the 8156 RM, both MAPLE-B and QUICC Engine have Dual RISC Engine. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In 8156 PB, on page 11, it says &amp;nbsp;&lt;/P&gt;&lt;P&gt;The QUICC Engine subsystem includes dual RISC processors and 48-Kbyte multi-master RAM&lt;BR /&gt;to handle the Ethernet and SPI interfaces, thus off loading the tasks from the cores. The three&lt;BR /&gt;communication controllers support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 01 May 2010 02:48:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196767#M1828</guid>
      <dc:creator>starcoreDSP</dc:creator>
      <dc:date>2010-05-01T02:48:03Z</dc:date>
    </item>
    <item>
      <title>Re: Dual RISC processor in MSC8156</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196768#M1829</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, Thank you.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 01 May 2010 21:12:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Dual-RISC-processor-in-MSC8156/m-p/196768#M1829</guid>
      <dc:creator>lpeng</dc:creator>
      <dc:date>2010-05-01T21:12:04Z</dc:date>
    </item>
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