<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic PCIe occur polling.compliance error on S32R45 in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/PCIe-occur-polling-compliance-error-on-S32R45/m-p/1665708#M18065</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; On our S32R45 board, the REFCLK of PCIe_1 have connect to external 100MHz clock, and setenv hwconfig "pcie0:mode=ep,clock=int;pcie1:mode=rc,clock=ext" in uboot.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Reboot the system,&amp;nbsp;PCIe_1 occur polling.compliance error.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; atf version: release/bsp33.0-2.5&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; uboot version:&amp;nbsp;release/bsp33.0-2020.04&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; linux version:&amp;nbsp;release/bsp33.0-5.10.109-rt&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="aiweixin_0-1686189579454.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226736i65FAC22EFF948DEC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="aiweixin_0-1686189579454.png" alt="aiweixin_0-1686189579454.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;SPAN&gt;Why? and how to make it ok?&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 08 Jun 2023 02:04:02 GMT</pubDate>
    <dc:creator>aiweixin</dc:creator>
    <dc:date>2023-06-08T02:04:02Z</dc:date>
    <item>
      <title>PCIe occur polling.compliance error on S32R45</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/PCIe-occur-polling-compliance-error-on-S32R45/m-p/1665708#M18065</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; On our S32R45 board, the REFCLK of PCIe_1 have connect to external 100MHz clock, and setenv hwconfig "pcie0:mode=ep,clock=int;pcie1:mode=rc,clock=ext" in uboot.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Reboot the system,&amp;nbsp;PCIe_1 occur polling.compliance error.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; atf version: release/bsp33.0-2.5&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; uboot version:&amp;nbsp;release/bsp33.0-2020.04&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; linux version:&amp;nbsp;release/bsp33.0-5.10.109-rt&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="aiweixin_0-1686189579454.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226736i65FAC22EFF948DEC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="aiweixin_0-1686189579454.png" alt="aiweixin_0-1686189579454.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;SPAN&gt;Why? and how to make it ok?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Jun 2023 02:04:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/PCIe-occur-polling-compliance-error-on-S32R45/m-p/1665708#M18065</guid>
      <dc:creator>aiweixin</dc:creator>
      <dc:date>2023-06-08T02:04:02Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe occur polling.compliance error on S32R45</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/PCIe-occur-polling-compliance-error-on-S32R45/m-p/1665869#M18069</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Please submit a ticket at nxp.com so I can escalate this question to RADAR team.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/HomeTest-Knowledge-Base/How-to-submit-a-new-question-for-NXP-Support/ta-p/1117058" target="_blank"&gt;https://community.nxp.com/t5/HomeTest-Knowledge-Base/How-to-submit-a-new-question-for-NXP-Support/ta-p/1117058&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Thu, 08 Jun 2023 06:08:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/PCIe-occur-polling-compliance-error-on-S32R45/m-p/1665869#M18069</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2023-06-08T06:08:26Z</dc:date>
    </item>
  </channel>
</rss>

