SPI's CPHA description in NXP's Block Guide

Sophie5387 — Sat, 27 May 2023 09:45:10 GMT

I'm a little confused about the CPHA description on the SPI Block Guide V04.01 from Motorola/NXP. The description is the following:

"If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register mythdhr, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit."

My confusion is about why using different clock edges (I mean rising vs. falling or vice-versa) to latch the serial data input and shift it into the shift register. What does motivate this behavior? Doesn't it make a configurable master device much more complicated? Doesn't it make STA more complicated as well? I did some sketches here and it seems to be possible to use the same clock edge to latch the serial input data and to shift it into the shift register without any penalty...

Re: SPI's CPHA description in NXP's Block Guide

RaRo — Mon, 05 Jun 2023 21:00:42 GMT

Hello @Sophie5387,

First of all, could you please tell us which microcontroller are you using or referring to?

We recommend you use the SPI as mentions in the SPI Block Guide V4. The usage of latching and then shifting the data in different clock edges could be to prevent delay skews, and other possible errors in the data transmission.

Best regards, Raul.

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SPI's CPHA description in NXP's Block Guide

Re: SPI's CPHA description in NXP's Block Guide