Other NXP Products中的主题 Re: P1013 Performance Monitor Event codes

P1013 Performance Monitor Event codes

TKing — Wed, 02 Nov 2022 17:48:11 GMT

I've searched everywhere here and on the internet. I cannot find a list of the P1013/P1022 Performance Monitor events codes. Many references to the "e500 Ref Man" but any I've found does not have accurate event values.

I can get the monitor to count events - I just don't know what it is counting.

I'm looking for the codes for instructions executed and L1 cache reloads.

Re: P1013 Performance Monitor Event codes

yipingwang — Thu, 10 Nov 2022 07:16:22 GMT

The DDR Memory Controller Perfmon event "Reads or writes from core" refers to both data and instruction transactions (this is clarified in the Reference Manual). And in general, all of the DDR Memory Controller events that are "Reads or write from...." should be counters of the number of DDR Controller transactions issued. That is, a 32-byte cache line transaction will count as 1. 32 individual byte accesses (if not coalesced) will count as 32.

Regarding the L2 Cache/SRAM Perfmon event "Core data accesses to L2 that miss", yes, both reads and writes are counted. Also, anything that is not a L2 hit is considered a L2 Miss (including cache-inhibited transactions), and that once again, this counts on a per-cacheline transaction basis. So, a single cache line burst transfer will increment the count by 1."

Re: P1013 Performance Monitor Event codes

TKing — Thu, 10 Nov 2022 13:24:09 GMT

Yes, thanks for your reply.

Unfortunately, I already understand all of the info that you provided about how the caches work. But that was not the question I asked.

I have read the section of the P1022/P1013 (section 25) manual and understand how the Performance Monitor is setup using the 'A' and 'B' control registers for the particular counter. In those registers an Event field is used to select the particular thing to count. In the “PowerPC™ e500 Core Family Reference Manual” in table 7-10 there are event entries:
1) Ref:2 – Instructions completed
2) Com:60 - Instruction L1 cache reloads from fetch

Per the manual the Ref and Com events code should be available to e500 architectures for the PMC0 to PMC3 counters. The P1013 is a Power PC with a single e500 core so I should be able to use these to determine L1 Cache miss rate. In fact the Event Description for the reload Event says exactly that “Typically used to determine instruction cache miss rate (along with instructions completed)”.

I have tried using the two event code above but nothing counts. I have looked in the P1022/P1013 (section 25) manual and there are no event codes that mirror the ones in the e500 manual.

My question is: what are the Performance Monitor event codes for "instructions executed" and "L1 cache reloads".

Re: P1013 Performance Monitor Event codes

yipingwang — Tue, 22 Nov 2022 05:39:52 GMT

please see section:

13.1.3.3 Scripting example

in:

https://www.nxp.com/docs/en/supporting-information/QorIQ-SDK-1.2-IC-RevA.pdf

Also see attachment AN3636

Re: P1013 Performance Monitor Event codes

TKing — Tue, 29 Nov 2022 13:22:26 GMT

Thanks for the information but that does not answer the question. I am not looking for source code. I'll repeat the question here but first I will try to give some background that could narrow the search for you.

I am trying to analyze the number of L1 cache misses that are occurring in my application. I need to know what values (numbers) I put in the event code field of the performance monitor control registers. They are documented in "P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013" on pages 1963 and 1964. The fields for these registers (PERFMON_PMLCA1, PERFMON_PMLCA2, PERFMON_PMLCA3, etc.) are described on page 1969. The particular field I am asking about is:

Bits: 9-15
Field: EVENT
Description: Event selector. Up to 128 events selectable. Note that with counter-specific events, an offset of 64 must be used when programming the field, because counter-specific events occupy the bottom 64 values of the 7-bit event field where events are numbered. For example, to specify counter-specific event 0, the event field must be programmed to 64. See Table 25-43 for definition of events.

If you look at Table 25-43 starting on page 1978 there are a series of numbers for different events that show what is counted for each EVENT CODE.

So that leads to the question I am asking: What are the Performance Monitor event codes for "instructions executed" and "L1 cache misses"?