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    <title>topic Re: s32r45 u-boot GPIO configuration in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1478197#M14427</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;I have asked our R45 application engineer for help.&lt;/P&gt;
&lt;P&gt;Once I have any answer I will feedback you.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
    <pubDate>Wed, 22 Jun 2022 12:44:52 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2022-06-22T12:44:52Z</dc:date>
    <item>
      <title>s32r45 u-boot GPIO configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1476759#M14405</link>
      <description>&lt;P&gt;s32r45's gmac default is 'rgmii' so that gmac0 tx clock is currently output.&lt;/P&gt;&lt;P&gt;We should change tx clock as input in order to use 'mii'&lt;/P&gt;&lt;P&gt;Accordingly, s32r45-pinctrl.h file has been changed as follow&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="eddy_bts_0-1655722805758.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/183898i6EA38EE2955B4BE8/image-size/large?v=v2&amp;amp;px=999" role="button" title="eddy_bts_0-1655722805758.png" alt="eddy_bts_0-1655722805758.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In T32, modification above is not applied to register&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="eddy_bts_1-1655722928371.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/183899iC4931F16A740E8C0/image-size/large?v=v2&amp;amp;px=999" role="button" title="eddy_bts_1-1655722928371.png" alt="eddy_bts_1-1655722928371.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Any advice?&lt;/P&gt;</description>
      <pubDate>Mon, 20 Jun 2022 11:02:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1476759#M14405</guid>
      <dc:creator>eddy_bts</dc:creator>
      <dc:date>2022-06-20T11:02:24Z</dc:date>
    </item>
    <item>
      <title>Re: s32r45 u-boot GPIO configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1478197#M14427</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;I have asked our R45 application engineer for help.&lt;/P&gt;
&lt;P&gt;Once I have any answer I will feedback you.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jun 2022 12:44:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1478197#M14427</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2022-06-22T12:44:52Z</dc:date>
    </item>
    <item>
      <title>Re: s32r45 u-boot GPIO configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1478377#M14429</link>
      <description>&lt;P&gt;Hi Eddy,&lt;/P&gt;
&lt;P&gt;I just tried this out on BSP32 and it seems to work:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="alejandrolozan1_0-1655920535195.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/184294i9A7309C4C9273F4A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="alejandrolozan1_0-1655920535195.png" alt="alejandrolozan1_0-1655920535195.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The change you made is exactly the one I did on Uboot:&lt;/P&gt;
&lt;P&gt;diff --git a/include/dt-bindings/pinctrl/s32r45-pinctrl.h b/include/dt-bindings/pinctrl/s32r45-pinctrl.h&lt;BR /&gt;index 3a80e52925..5c60a6f030 100644&lt;BR /&gt;--- a/include/dt-bindings/pinctrl/s32r45-pinctrl.h&lt;BR /&gt;+++ b/include/dt-bindings/pinctrl/s32r45-pinctrl.h&lt;BR /&gt;@@ -251,7 +251,7 @@&lt;BR /&gt;/* PE02 */&lt;BR /&gt;#define PE02_MSCR_S32R45 (66)&lt;BR /&gt;#define PE02_GMAC0_TX_CLK_CFG (SIUL2_MSCR_S32_G1_MUX_ID_1 | \&lt;BR /&gt;- ENET_CLK_PIN_CFG)&lt;BR /&gt;&lt;STRONG&gt;+ ENET_IN_PIN_CFG)&lt;/STRONG&gt;&lt;BR /&gt;#define PE02_GMAC0_TX_CLK_IN (SIUL2_MSCR_S32_G1_MUX_ID_2)&lt;/P&gt;
&lt;P&gt;/* PE03 */&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;I just rebuild uboot:&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;make s32r45evb_defconfig&lt;/P&gt;
&lt;P&gt;make CROSS_COMPILE=/&amp;lt;To toolchain path&amp;gt;/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Rebuild ATF:&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;make CROSS_COMPILE=/&amp;lt;To toolchain path&amp;gt;/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu- ARCH=aarch64 PLAT=s32r45evb BL33=/&amp;lt;To Uboot Path&amp;gt;/u-boot/u-boot-s32.bin&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;And flashed the fip.s32&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;sudo dd if=fip.s32 of=/dev/mmcblk0 skip=512 seek=512 iflag=skip_bytes oflag=seek_bytes conv=fsync,notrunc&lt;/P&gt;
&lt;P&gt;If you are following these steps it is likely that the image is not being updated.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Saludos,&lt;/P&gt;
&lt;P&gt;Alejandro&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jun 2022 17:59:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1478377#M14429</guid>
      <dc:creator>alejandrolozan1</dc:creator>
      <dc:date>2022-06-22T17:59:52Z</dc:date>
    </item>
    <item>
      <title>Re: s32r45 u-boot GPIO configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1481477#M14489</link>
      <description>&lt;P&gt;Thanks. It was my miss. I works well&lt;/P&gt;</description>
      <pubDate>Wed, 29 Jun 2022 02:35:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/s32r45-u-boot-GPIO-configuration/m-p/1481477#M14489</guid>
      <dc:creator>eddy_bts</dc:creator>
      <dc:date>2022-06-29T02:35:16Z</dc:date>
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