Other NXP ProductsのトピックRe: SPI Configuration for Controller MWCT2013A

SPI Configuration for Controller MWCT2013A

ramesh_chand — Tue, 19 Apr 2022 12:14:14 GMT

Hi Team,

i'm trying to configure QSPI in MWCT2013A Controller.

i'm not able to find Pseudo code/ Application note for the configuration.

i have tried below configuration and shorted MOSI and MISO lines to observe whether the sent data and data in receive buffer are same or not.

if i send 0xAB data i'm observing different data in QSPI0_SPDRR register.

void SPI_init(void) { /* Enable SPI1 Clock */ SIM->PCE1 |= (0x0200U); // SIM_PCE1 : 9th bit /*Configure the Peripheral Functionality to be used as SPI on the selected PORT */ SIM->GPSCL |= 0x0000U ; // SIM_GPSCL :SEL SPI mode bits set to 00 SIM->GPSCH |= 0x0000U; // SIM_GPSCH :SEL SPI mode bits set to 00 /*The Port GPIO are configured for peripheral mode */ GPIOC->PER |= (0x0780U); // C7, C8,C9,C10 set to peripheral mode // Baudrate setting QSPI0->SPSCR &= ~QSPI_SPSCR_SPR_MASK; QSPI0->SPSCR |= QSPI_SPSCR_SPR(0x1); // Baudrate = 100Mhz/4 = 25MHz QSPI0->SPDSR &= ~(QSPI_SPDSR_BD2X_MASK|QSPI_SPDSR_SPR3_MASK); // BD2X=0, SPR3 = 0 QSPI0->SPSCR &= ~QSPI_SPSCR_CPHA_MASK; // CPHA = 0, slave data is ready when SS falls down QSPI0->SPSCR &= ~QSPI_SPSCR_CPOL_MASK; // CPOL = 0 // Data size QSPI0->SPSCR &= ~QSPI_SPSCR_DSO_MASK; // MSB first QSPI0->SPSCR |= QSPI_SPSCR_SPMSTR_MASK; // Master mode QSPI0->SPDSR &= ~QSPI_SPDSR_SSB_AUTO_MASK; // software generated SS signal QSPI0->SPDSR &= ~QSPI_SPDSR_DS(0xE); QSPI0->SPDSR |= QSPI_SPDSR_DS(0x7); // 8 bits in one transaction // Enable SPI QSPI0->SPSCR |= QSPI_SPSCR_SPE_MASK; } void SPI_Send(uint8_t uw8Data) { while((QSPI0->SPSCR & 0x0001) == 0){} // SPTE == 0 indicates busy // Write data to SPI transmit data register QSPI0->SPDTR = uw8Data; // Wait till SPTE == 1 while((QSPI0->SPSCR & 0x0008) == 0){} // SPRF == 0 indicates busy }

Could you please provide any other document other than reference manual or help me to identify where i'm going wrong in the above configuration.

If we want to configure SPI FIFO register is there any pseudo code available for this?

Thank You,

Re: SPI Configuration for Controller MWCT2013A

xiangjun_rong — Wed, 20 Apr 2022 06:21:31 GMT

Hi,

Pls try to use the following code:

void SPI_init(void)
{
/* Enable SPI1 Clock */
SIM->PCE1 |= (0x0200U); // SIM_PCE1 : 9th bit
/*Configure the Peripheral Functionality to be used as SPI on the selected PORT */
SIM->GPSCL &=~(0xC000U); // SIM_GPSCL :SEL SPI mode bits set to 00
SIM->GPSCH &= ~(0x003FU); // SIM_GPSCH :SEL SPI mode bits set to 00

/*The Port GPIO are configured for peripheral mode */
SIM->PCE0 |= (0x10U); // SIM_PCE0 : 4th bit, enable GPIOC port
GPIOC->PER |= (0x0780U); // C7, C8,C9,C10 set to peripheral mode
#if 0
// Baudrate setting
QSPI0->SPSCR &= ~QSPI_SPSCR_SPR_MASK;
QSPI0->SPSCR |= QSPI_SPSCR_SPR(0x1); // Baudrate = 100Mhz/4 = 25MHz
QSPI0->SPDSR &= ~(QSPI_SPDSR_BD2X_MASK|QSPI_SPDSR_SPR3_MASK); // BD2X=0, SPR3 = 0
QSPI0->SPSCR &= ~QSPI_SPSCR_CPHA_MASK; // CPHA = 0, slave data is ready when SS falls down
QSPI0->SPSCR &= ~QSPI_SPSCR_CPOL_MASK; // CPOL = 0

// Data size
QSPI0->SPSCR &= ~QSPI_SPSCR_DSO_MASK; // MSB first
QSPI0->SPSCR |= QSPI_SPSCR_SPMSTR_MASK; // Master mode

QSPI0->SPDSR &= ~QSPI_SPDSR_SSB_AUTO_MASK; // software generated SS signal
QSPI0->SPDSR &= ~QSPI_SPDSR_DS(0xE);
QSPI0->SPDSR |= QSPI_SPDSR_DS(0x7); // 8 bits in one transaction
#endif
// Enable SPI
QSPI0->SPSCR =0x0100; //master mode, MSB first, CPOL=CPHA=0, polling mode is used
QSPI0->SPDSR=0x01CF; //16 bits data,
QSPI0->SPSCR |= QSPI_SPSCR_SPE_MASK;
}

void SPI_Send(uint8_t uw8Data)
{
while((QSPI0->SPSCR & 0x0001) == 0){} // SPTE == 0 indicates busy

// Write data to SPI transmit data register
QSPI0->SPDTR = uw8Data;

// Wait till SPTE == 1
while((QSPI0->SPSCR & 0x0008) == 0){} // SPRF == 0 indicates busy

}

Hope it can help you

XiangJun Rong

Re: SPI Configuration for Controller MWCT2013A

ramesh_chand — Wed, 20 Apr 2022 13:43:33 GMT

Thank you for the reply XiangJun.

i'll try let you know..