topic Re: PLL / DLL clock unstable at -10C in Other NXP Products

PLL / DLL clock unstable at -10C

pdoan — Tue, 08 Nov 2011 05:52:04 GMT

Hi,

I am trying to debug an intermittent boot up failure starting at -5C degree in our production system with using MPC8270. During the debugging, we find out that when the system failed to boot up at -10C, the DLL output is jumping and very unstable which causes the corruption of the load/store instructions to/from SDRAM.

In our system, we have the clock configure mode as PCI agent mode with the PCI clock (66MHz) feed into the clkin1 (as figure 10-2 on section10.1.6 of the MPC8270 Reference Manual) with the clock configure mode as: MODCK_H=0110, MODCK[1-3]=001 and PCI_MODCK=0.

I looked into mpc8280 errata on the PLL/DLL jitter but didn't found any thing that could cause the PLL/DLL clock is jittering/unstable jumping. I wonder if anyone using this device has seen the PLL behavior like this before? Please help.

Also, when I search for this problem, there is an errata "PNC14620" that talk about the PLL supply voltage filter problem. Could someone tell me how big of the noise on the PLL supply voltage (VCCSYNC1) that this errata referred to?

Thanks for your help

--Phuong

Re: PLL / DLL clock unstable at -10C

TomE — Tue, 08 Nov 2011 12:46:12 GMT

MPC8270 or MPC8270C? The MPC8270 is only specified down to 0C. The MPC8270C goes down to -40C.

If you are using the "Extended Range" chip, is the clkin1 signal still stable (good levels, duty cycle, edges) at low temperatures?

Try heating different components. Is it the CPU itself that is the most temperature sensitive? Heat whatever is providing the clock signal. Heat your bypass caps and power supply components.

Tom

Re: PLL / DLL clock unstable at -10C

pdoan — Wed, 09 Nov 2011 03:33:11 GMT

Hi Tom,

Thanks for the quick response. We are using MPC8270CZUUPEA which is the industrial part that goes down to -40C. Yes, we monitor the clkin1 and it's stable in voltage level, duty cycle and edge at -10C when 8270 is hanging. The only clock jumping are the DLL out which is the output clock from the DLL clock module of the 8270 and the clkin2. This clkin2 is generated from the DLL out clock through a clock buffer and feed back to the 8270 clkin2 IO pin.

--Phuong

Re: PLL / DLL clock unstable at -10C

alexander_yakov — Wed, 09 Nov 2011 13:28:27 GMT

Dear Phuong

Please open a Service Request to tech support and attach your schematics, I will look how VCCSYN filtering is implemented in your case and other related circuits.

If possible, please also attach scope or logic analyzer pictures illustrating the problem, just to understand what exactly happening.

Re: PLL / DLL clock unstable at -10C

dank4 — Thu, 03 Dec 2015 06:07:41 GMT

Phuong Hi ,

have you got a solution to the problem ?

We are suffering from a very similar problem in few of our projects, we got a stuck CPU at different temp. and cases.

I would thank your reply-how was the issue dealt with.

Thanks

Dan