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SGTL5000 ADC SNR when simultaneously using DAC

aidyw — Fri, 10 Dec 2021 15:51:11 GMT

Hi,

I'm working with the SGTL5000. I have used this codec a few times in various projects and every time I have had mixed results when it comes to the noise levels from the ADC. I am looking for some more detailed information about methods I might try to improve the SNR from the ADC.

In my current project I have been very methodical about measuring the ADC performance under various conditions and I have run up against a situation I can not seem to resolve. I would invite any responses to point me in a new direction.

Please allow me to explain how I am using the IC in order that we are clear what I have done up to this point:

The SGTL5000 is logically split into 2 halves. The ADC drives I2S out to a DSP and the DSP then sends I2S back into the SGTL5000 to employ its DAP, DAC and HP amplifiers.

From a grounding perspective I am using split digital and analog ground planes, but the SGTL5000 is entirely located within the analog plane. That is to say, I have the AGND and DGND pins both connected locally under the SGTL5000 IC, this is then taken through a low impedance path to the analog GND plane. (Please note I have also tried coupling the DGND pin to the digital GND plane, but this causes even worse performance).

The SGTL5000 is supplied with separate power supplies, all initially derived from a common 12V DC source:

VDDIO is running from the 3.3V digital supply shared with the external DSP which is derived from a local drop down buck converter followed by an LDO.

VDDD is supplied from 1.8V local linear reg. derived from the VDDIO supply locally decoupled and located within a few mm of the IC pins.

Both VDDIO and VDDD are both locally and independently filtered and decoupled with 2.2uF and 100nF caps and furthermore the incoming 3.3V from the external supply is resistivity isolated using a 10ohm resistor before the local smoothing and decoupling caps and (VDDD) LDO. This is done to ensure that and digital switching currents local to the SGTL5000 can find a return current path directly to the local capacitors and should not extend out through the analog GND plane.

VDDA is supplied from a totally independent power supply derived from a separate drop down buck converter and LDO combination. This is highly filtered using RLC low pass with a corner frequency down at ~ 1Khz and further isolated within a few mm of the IC pins using a ferrite bead and local smoothing and decoupling. (It is clean with < 2mV of ripple and a noise level well below 100dBV. So low I cant measure it with my passive scope leads).

From this starting point I doubt I can offer the IC any better to allow it to achieve stated performance.

Note: the following tests are carried out with ADC, DAC and HP modules powered up. Lineout is power down.

Under these conditions I began measuring the ADC performance. Initially I do not send any I2S data into the SGTL5000 (DIN sitting at zero volts), instead simply using the ADC > I2Sout path.

This delivers expected max performance. with 85dB SNR when the ADC inputs are floated. (Max 1.8 bits of noise). And the same performance if both the ADC pins are de-coupled to AGND with a huge 10uF cap.

If I then configure the HP amplifier to be fully turned down, (CHIP_ANA_HP_CTRL:HP_VOL_RIGHT & HP_VOL_LEFT = 0x7F), and start sending full scale I2S data into DIN. I see a slight reduction in ADC performance, with now ~ 3bits of noise. ~78dB SNR.

Now the crunch. If I turn up the HP amplifier from -51dB all the way to +12dB:
This increases the ADC noise to a maximum of: ~ 3.5bits on the Left channel and a whopping ~9.5bits ~39dB noise on the Right channel. When the inputs are floating.
If I de-couple the R ADC channels to AGND with 10uF, I can reduce this noise on the right channel to similar levels to the left channel. Strange but hey..

With this configuration both ADC channels now perform almost identically:
I see a slight increase in ADC noise in direct proportion to the HP amplifier output level, up to the point of 0dB HP gain at which point the ADC SNR ~70dB. Then a dramatic rise in ADC noise when the HP amplifiers begin to clip with +ve gains up to a point where HP +12dB gives ADC noise of ~66dB.

I also tested with the HP module powered down and instead the Line-out module powered UP. The results are very similar. With slightly less impact on the Left ADC channel.

I have 2 SGTL5000 ICs on the board and both demonstrate exactly the same behaviour.

Finally and it would seem rather conclusive test. I power down the DAC module. Under these conditions both channels on the ADC deliver datasheet ideal ~85dB performance.
It would appear that using the DAC has a direct and significant impact on ADC performance.

Is this an accepted truth from NXP, and if not how might I mitigate this problem?

Re: SGTL5000 ADC SNR when simultaneously using DAC

JozefKozon — Mon, 13 Dec 2021 09:10:49 GMT

Hi Aidan,

yes, this is a known issue.

Please try to decrease the “DAC Digital Volume Control” (-19.1dB should work, but if you still hearing the noise try to use -38.1dB).

With Best Regards,

Jozef

Re: SGTL5000 ADC SNR when simultaneously using DAC

aidyw — Mon, 13 Dec 2021 15:01:39 GMT

Hi Jozef,

Thanks for the reply.

If you are suggesting I turn down the DAC, how am I to obtain any useful analog output level?

Can you clarify how this works internally. Does the DAC volume control sit within the digital or anlog domain of the IC. That is to say, is the DAC volume a digital scaling done before the DAC process. If so by turning down the DAC I will loose resolution? Or is the DAC volume an analog amplifier after the DAC ouput and before either HP or Line-out amplifiers.

In either case if I turn down the DAC level I must at some stage make up this gain within the analog domain. This sounds a little like 'kicking the can down the road'. It will inevitably reduce the SNR of the chain.

Can you give further information when you state, this is a known issue. What exactly is happening, is this noise coupling occurring within the IC?

Are you therefore suggesting that to entirely overcome the problem, I must use an external DAC and as a consequence if I require to use the DAP features in this case, they must be applied pre-processed, before data is sent out of the SGTL5000 on its I2S interface?

All the best

Aidan

Re: SGTL5000 ADC SNR when simultaneously using DAC

aidyw — Mon, 13 Dec 2021 17:47:06 GMT

Hi Jozef,

Just for completeness I tested the effect of modulating the DAC volume as you suggested.

Indeed the majority of the ADC noise seems related to the DAC volume. That is to say:

When DAC volume set 0 (fully muted), the ADC when decoupled to AGND through 10uF displays a SNR ~ 79dB

When DAC volume set to 1 (full scale), the ADC display a SNR ~69dB.

This is with the HP module power on or off, it has minimal effect. However if the HP module is powered on and the HP gain goes above 0dB with a full scale DAC input (i.e. HP clipping), the ADC SNR suffers further and becomes ~66dB.

But it does seem that the DAC volume is the primary source of the ADC perturbations. Though we still seem to have a base level reduction of SNR from (86dB DAC oof) - (79dB DAC on) = ~7dB simply by having the DAC module powered on. Regardless of the DAC volume setting.

Aidan