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    <title>topic Need clarification about QSPI in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/Need-clarification-about-QSPI/m-p/1323691#M11803</link>
    <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/152930i11F870CAC528F4CF/image-size/large?v=v2&amp;amp;px=999" role="button" title="Capture.JPG" alt="Capture.JPG" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Capture.JPG&lt;/span&gt;&lt;/span&gt;we are not used NAND and NOR flash, we are using QSPI and eMMC flash in LS1043A processor. NOR and NAND flash is mandatory for LS1043A??&lt;/P&gt;&lt;P&gt;if not&amp;nbsp;mandatory ,how to configure the IFC pin?? like AD1 to A25,CLE, AVD etc.....&lt;/P&gt;&lt;P&gt;consider the above image. it is our current design.&amp;nbsp;is it is ok????&lt;/P&gt;</description>
    <pubDate>Mon, 16 Aug 2021 05:47:37 GMT</pubDate>
    <dc:creator>manid</dc:creator>
    <dc:date>2021-08-16T05:47:37Z</dc:date>
    <item>
      <title>Need clarification about QSPI</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Need-clarification-about-QSPI/m-p/1323691#M11803</link>
      <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/152930i11F870CAC528F4CF/image-size/large?v=v2&amp;amp;px=999" role="button" title="Capture.JPG" alt="Capture.JPG" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Capture.JPG&lt;/span&gt;&lt;/span&gt;we are not used NAND and NOR flash, we are using QSPI and eMMC flash in LS1043A processor. NOR and NAND flash is mandatory for LS1043A??&lt;/P&gt;&lt;P&gt;if not&amp;nbsp;mandatory ,how to configure the IFC pin?? like AD1 to A25,CLE, AVD etc.....&lt;/P&gt;&lt;P&gt;consider the above image. it is our current design.&amp;nbsp;is it is ok????&lt;/P&gt;</description>
      <pubDate>Mon, 16 Aug 2021 05:47:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Need-clarification-about-QSPI/m-p/1323691#M11803</guid>
      <dc:creator>manid</dc:creator>
      <dc:date>2021-08-16T05:47:37Z</dc:date>
    </item>
    <item>
      <title>Re: Need clarification about QSPI</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/Need-clarification-about-QSPI/m-p/1323885#M11805</link>
      <description>&lt;P&gt;You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; NOR and NAND flash is mandatory for LS1043A?&lt;/P&gt;&lt;P&gt;Not mandatory.&lt;/P&gt;&lt;P&gt;&amp;gt; how to configure the IFC pin?? like AD1 to A25,CLE, AVD etc..&lt;/P&gt;&lt;P&gt;Please refer to the AN5012 - QorIQ LS1043A Design Checklist, Table 10. IFC pin termination checklist.&lt;/P&gt;</description>
      <pubDate>Mon, 16 Aug 2021 10:49:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/Need-clarification-about-QSPI/m-p/1323885#M11805</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-08-16T10:49:46Z</dc:date>
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