topic Re: MC34VR500V4ES and LS1043A power down sequencing in Other NXP Products

MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Mon, 26 Jul 2021 06:01:59 GMT

Hi,

MC34VR500V4ES is particularly designed for power on sequencing LS1043A layerscape processor.

the power down sequencing of the particular PMIC is not explained in the datasheet.

since there are a lot of rails in the MC34, which all rails will be powered down and what is the sequence of power down.

what is the power down sequence of LS1043A and MC34VR500..?

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Thanks & Regards,

Akshay V

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Mon, 26 Jul 2021 07:00:38 GMT

No power down sequence!

Re: MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Mon, 26 Jul 2021 09:32:46 GMT

what happens when EN of MC34VR500V4ES is pulled low..?

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Mon, 26 Jul 2021 11:04:21 GMT

The EN pin is used to power off the 34VR500. The Off mode is entered when the EN pin is low and SWxOMODE = 0.

Re: MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Mon, 26 Jul 2021 13:03:53 GMT

so in order to turn off, we have to use both EN and SWxMode..?

Which all rails are turning off one by one..

whether the rails turn off sequence doesnt affect the LS1043..?

what happens if the processor is doing some processing and how would the processor core rail turn off last..?

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Mon, 26 Jul 2021 13:13:16 GMT

SWxOMODE default value is 0 as OFF.

Re: MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Tue, 27 Jul 2021 07:11:05 GMT

Are you saying that there is no power off sequence for LS1043A..?

Every processor may be working in some tasks, so when we pull the EN low, how can the processor can be turned off when it is carrying out some tasks..?

wont it require a signalling of power off sequence request and after the confirmation from the processor to continue the power off procedure, then only should the power off to be carried out.

And also, every processor will be having core power and auxiliary rails . so incase of a power down, this core must be turned off last and all the auxiliary rails must be turned off one by one, rather than shuting down every rail spontaneously.

cant get the logic in this.

So, what exactly happens when the power is turned off in MC34VR500V4ES(ie, EN pulled low)

will it suddenly stop working..?

is that acceptable for a networking processor..?

Please explain in detail the process of turn off procedure of LS1043 and how MC34VR500 accomodates this necessities.

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Thanks & regards,

Akshay V

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Tue, 27 Jul 2021 07:51:41 GMT

Enter OFF state of PMIC when EN is low and keep default of SWxOMODE bits.

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Tue, 27 Jul 2021 07:59:24 GMT

For more detail information about LS1043A side power requirement questions please reply based on your case 00382309.

Re: MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Tue, 27 Jul 2021 10:40:08 GMT

Hi,

we require to know right now is how MC34VR500 handles the power down requirements of LS1043A.

the power down sequencing of MC34VR500 when the EN is pulled low is the information that we require.

Since MC34VR500V4ES is for specific function of powering up and down LS1043A, it should also be applicable for Power down sequencing, right..?

So, what is the sequence of power down of MC34VR500V4ES.

Which all SW's and LDO's are powered down and what are the sequence of this power down.

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Thanks & Regards,

Akshay V

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Wed, 28 Jul 2021 02:41:46 GMT

For 34VR500,when it enters the OFF mode after a turn-off event. A thermal shutdown event also forces the 34VR500 into the OFF mode. Only VDIG is powered in this mode of operation.

Re: MC34VR500V4ES and LS1043A power down sequencing

Akshayv — Wed, 28 Jul 2021 03:59:00 GMT

which LDO's and SW are powered down and what is the sequence of this power down..?

what is the power down procedure for MC34.

What is the exact role od SWxOMode and EN.

whether EN is only required for Power down..?

also, please explain the power down sequencing how cops with LS1043A

explanation is required rather than single line answers

Re: MC34VR500V4ES and LS1043A power down sequencing

guoweisun — Wed, 28 Jul 2021 07:42:49 GMT

1:which LDO's and SW are powered down and what is the sequence of this power down..?

[1]No power down sequence, set SWxOMode as default when EN is low,the rails power down at same time ,only VDIG is ON.

2:also, please explain the power down sequencing how cops with LS1043A

explanation is required rather than single line answers.

[2]For LS1043A side,please ask based on your case 00382309,because this case take over by LS1043A team,I only support PMIC side.