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    <title>Other NXP ProductsのトピックLS1046A PDN design</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295384#M11328</link>
    <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;I would like to optimize decoupling capacitor around LS1046A. Please let me know the instantaneous&amp;nbsp; current profile drawn by LS1046A.&lt;/P&gt;&lt;P&gt;Also it would be nice if you can share documents related LS1046A PDN design.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Naresh V.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 21 Jun 2021 10:57:54 GMT</pubDate>
    <dc:creator>Nareshvarikuntla</dc:creator>
    <dc:date>2021-06-21T10:57:54Z</dc:date>
    <item>
      <title>LS1046A PDN design</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295384#M11328</link>
      <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;I would like to optimize decoupling capacitor around LS1046A. Please let me know the instantaneous&amp;nbsp; current profile drawn by LS1046A.&lt;/P&gt;&lt;P&gt;Also it would be nice if you can share documents related LS1046A PDN design.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Naresh V.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jun 2021 10:57:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295384#M11328</guid>
      <dc:creator>Nareshvarikuntla</dc:creator>
      <dc:date>2021-06-21T10:57:54Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A PDN design</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295443#M11335</link>
      <description>&lt;P&gt;We do not have such a "current profile".&lt;/P&gt;
&lt;P&gt;Please take a look at AN5252 application note ("Design checklist", can be found on our web site), its section 4 provides power design recommendations.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Bulat&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jun 2021 13:02:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295443#M11335</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2021-06-21T13:02:55Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A PDN design</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295453#M11337</link>
      <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;I have already gone through AN5252. It doesn't have information on current profile and that is why I raised query in this forum.&lt;/P&gt;&lt;P&gt;NXP reference board has 8 layer. But I will be using board with more than 10 layers. In that I will allocate pair of layers for embedded capacitance so that I can reduce the decoupling capacitors and improve the component density.&lt;/P&gt;&lt;P&gt;So for this , I need the instantaneous current drawn by each power supply and their current profile. This information is missing in that datasheet or any other application notes.&amp;nbsp; Kindly share this information.&lt;/P&gt;&lt;P&gt;Also please do let me know how NXP decided on on number of decoupling capacitors and placement of capacitors for reference board. Kindly share relevant information.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jun 2021 13:17:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1295453#M11337</guid>
      <dc:creator>Nareshvarikuntla</dc:creator>
      <dc:date>2021-06-21T13:17:16Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A PDN design</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1296812#M11358</link>
      <description>&lt;P&gt;As I already wrote, we do not have documents with 'current profile'.&lt;/P&gt;
&lt;P&gt;To estimate current consuming by the cores and I/O interfaces, you can refer to data sheet. Tables 7 and 10 provides power numbers.&lt;/P&gt;
&lt;P&gt;If you take a look at the AN5252, you could find our recommendations about number of decouplng capacitors and their placement. Search for 'General Power supply decoupling' section.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Bulat&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jun 2021 10:35:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1296812#M11358</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2021-06-23T10:35:00Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A PDN design</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1296818#M11359</link>
      <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;Please do let me know how decoupling capacitors for LS1046RDB decided. Please share the simulations and Notes.&lt;/P&gt;&lt;P&gt;I believe this information will be available at least with the LS1046RDB board designer. Please share the information.&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jun 2021 10:43:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1046A-PDN-design/m-p/1296818#M11359</guid>
      <dc:creator>Nareshvarikuntla</dc:creator>
      <dc:date>2021-06-23T10:43:11Z</dc:date>
    </item>
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