Alternate Request

Jab_1 — Fri, 04 Jun 2021 14:36:45 GMT

Hi,

We are using the parts PTN3460BS/F6Y and PTN3460BS/F4Y in our projects, Due to unavailability issue of these two parts , we are checking the part PTN3460BS/F3 use as alternate for same project,

we could see the below mentioned major points new feature when checking the release note of PTN3460BS/F4Y,

*Implement DP one/two lane configurable setting in the configuration table (0x80
bit 2).
* Implement DP HRB/RBR or RBR only link rate configurable setting in the
configuration table (0x80 bit 3).

*Fix the backlight control function in the configuration table (0x95 bit 0) may not
work while system logout and log back in.
*Increase FW PLL range to +/- 6.25%.

I would like to get the full description of registers 0x95 and 0x80 for our reference and confirm to use as alternate , please share the description manual of above mentioned registers.

Also , I noticed from PTN3460, PTN3460I FAQs page in nxp community product form, that FW can be updated by flash over I2C , can you please confirm whether we can use the part TN3460BS/F3 as alternate for PTN3460BS/F6Y by update the firmware flash over I2C?.

Thanks,

Jabir

Re: Alternate Request

TomasVaverka — Tue, 08 Jun 2021 07:42:03 GMT

Hello Jabir,

Please see the answers inserted below in your text.

*Implement DP one/two lane configurable setting in the configuration table (0x80 bit 2).

>> If configuration register 0x80 bit 2 = 0, then PTN3460 will report to support DP 2 lanes configuration in the DPCD register 0x0002.

If configuration register 0x80 bit 2 = 1, then PTN3460 will report to support DP 1 lanes configuration in the DPCD register 0x0002.

* Implement DP HRB/RBR or RBR only link rate configurable setting in the configuration table (0x80 bit 3).

>> If configuration register 0x80 bit 3 = 0, then PTN3460 will report to support HBR (2.7Gbps) as max link rate in the DPCD register 0x0001.

If configuration register 0x80 bit 3 = 1, then PTN3460 will report to support RBR (1.62Gbps) as max link rate in the DPCD register 0x0001.

* Fix the backlight control function in the configuration table (0x95 bit 0) may not work while system logout and log back in.

>> if Configuration register 0x95 bit 0 = 0, then LCD backlight is ON.

If Configuration register 0x95 bit 0 = 1, then LCD backlight is OFF.

Users can use this bit to turn ON/OFF LCD backlight according to application needs, or just let PTN3460 control it in panel power on/off sequence.

*Increase FW PLL range to +/- 6.25%.

>> It is for fast detection DP link lost and turn off LCD panel backlight in time. So as long as incoming pixel clock is out of +/-6.25%, then PTN3460 will decide that DP link is lost (or unstable), and turn off LCD panel backlight, so that user will not see garbage video on LCD panel.

I would like to get the full description of registers 0x95 and 0x80 for our reference and confirm to use as alternate, please share the description manual of above mentioned registers.

Also, I noticed that FW can be updated by flash over I2C , can you please confirm whether we can use the part TN3460BS/F3 as alternate for PTN3460BS/F6Y by update the firmware flash over I2C?

>> Yes, it should possible, you should get more information on that in your case #00372681.

Best regards,

Tomas

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