Other NXP ProductsのトピックRe: srio tx from cacheable memory

srio tx from cacheable memory

s_kalop — Fri, 01 Jun 2012 12:45:21 GMT

Hello.

I use MSC8156ADS board and Spartan 6 connected to it by SRIO. Data transfers go by Ocean DMA succesfully only if memory blocks on MSC8156 is non-cacheable. But if the source address of ocnDMA transfer configuration is set for cacheable memory ocnDMA transmith zeros(digital loopback shows same result). I try to sweep cache for this memory but it is all the same. I see cacheable memory filled with true data while debugging, but ocnDMA transmits zeros.

How can i transmit by ocnDMA from cacheable memory? Thank you.

Re: srio tx from cacheable memory

yangjie — Sat, 02 Jun 2012 09:03:32 GMT

#if (MSC815X_OCN_DMA0 == ON)

ocn_dma_init_params_t ocn_dma_init_params0 =

{

OCN_DMA_ID0,

OS_HWI_PRIORITY0,

{

/* On which core to enable the channel. */

ANY_CORE_ID, ANY_CORE_ID, ANY_CORE_ID, ANY_CORE_ID,

{

RIO0_ATMU_BASE,

DMA_ATMU_WIN_SIZE,

OCN_DMA_INTERFACE_RIO0

{

RIO1_ATMU_BASE,

DMA_ATMU_WIN_SIZE,

OCN_DMA_INTERFACE_RIO1

{

M3_BASE_ADDR,

DMA_ATMU_WIN_SIZE,

OCN_DMA_INTERFACE_LOCAL1

}

};

the OCN-DMA channel depend on core.and cachable data is private for core.you can think about it.

Re: srio tx from cacheable memory

yangjie — Sat, 02 Jun 2012 09:32:21 GMT

os_config.h

#define num of core 1

then have a try .