<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Re:Facing issue on implementing the eDMA with DSPI peripheral in MPC5675KRM microcontroller in NXP Designs</title>
    <link>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159321#M765</link>
    <description>&lt;P&gt;Hi, I have been enabled the DMAMUX as follow,&lt;/P&gt;&lt;P&gt;DMAMUX_0.CHCONFIG[0].R = 0x00;&lt;BR /&gt;DMAMUX_0.CHCONFIG[0].R = 0x83;&lt;/P&gt;&lt;P&gt;to transmit data.&lt;/P&gt;</description>
    <pubDate>Fri, 25 Sep 2020 11:43:19 GMT</pubDate>
    <dc:creator>sachin_waghmare</dc:creator>
    <dc:date>2020-09-25T11:43:19Z</dc:date>
    <item>
      <title>Re:Facing issue on implementing the eDMA with DSPI peripheral in MPC5675KRM microcontroller</title>
      <link>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1158612#M760</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;I'm Sachin Waghmare,&lt;/P&gt;&lt;P&gt;I am using the MPC5675KRM microcontroller. We are facing issue on implementing the eDMA with DSPI peripheral&amp;nbsp;to transmit data over DSPI channel, I did't getting any clock pulse as well as data.&lt;/P&gt;&lt;P&gt;To transmit data through eDMA with DSPI peripheral the following sequence has been followed.&lt;/P&gt;&lt;P&gt;Kindly suggest if any thing is missed out in this sequence.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;void initDSPI_A(void)&lt;BR /&gt;{&lt;BR /&gt;DSPI_1.MCR.R = 0x80010001; /* Configure DSPI_A as master */&lt;BR /&gt;DSPI_1.RSER.R = 0x03030000; /* DMA enable */&lt;BR /&gt;DSPI_1.CTAR[0].R = 0x780A7727; /* Configure CTAR0, Baud rate 17.6kHz */&lt;BR /&gt;&lt;BR /&gt;DSPI_1.MCR.B.HALT = 0x0; /* Exit HALT mode: go from STOPPED to RUNNING state*/&lt;/P&gt;&lt;P&gt;/* Pad Config */&lt;BR /&gt;SIU.PCR[7].R = 0x0604; /* 7 sout, obe=1 */&lt;BR /&gt;SIU.PCR[8].R = 0x0504; /* 8 sin, ibe=1 */&lt;BR /&gt;SIU.PCR[6].R = 0x0604; /* 6 sck */&lt;BR /&gt;SIU.PCR[5].R = 0x0704; /* 5 cs0/ss */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;void eDMA_TCD_DSPI_Master_Transmit_init(void)&lt;BR /&gt;{&lt;BR /&gt;/*** source settings ***/&lt;BR /&gt;EDMA_0.TCD[2].SADDR = (vuint32_t) &amp;amp;DSPI_Master_Transmit_Data; // source address - command_word&lt;BR /&gt;EDMA_0.TCD[2].SSIZE = 2; // 32-bit&lt;BR /&gt;EDMA_0.TCD[2].SOFF = 4; // addr increment after transfer in bytes&lt;BR /&gt;EDMA_0.TCD[2].SLAST = 0; // after major loop, do not change&lt;BR /&gt;EDMA_0.TCD[2].SMOD = 0; // source modulo feature not used&lt;/P&gt;&lt;P&gt;/*** destination settings ***/&lt;BR /&gt;EDMA_0.TCD[2].DADDR = (vuint32_t) &amp;amp;DSPI_1.PUSHR.R; // dest. address - command PUSH register&lt;BR /&gt;EDMA_0.TCD[2].DSIZE = 2; // 32-bit&lt;BR /&gt;EDMA_0.TCD[2].DOFF = 0; // no addr increment after transfer&lt;BR /&gt;EDMA_0.TCD[2].DLAST_SGA = 0; // after major loop, do not change addr&lt;BR /&gt;EDMA_0.TCD[2].DMOD = 0; // destination modulo feature not used&lt;/P&gt;&lt;P&gt;/*** counts ***/&lt;BR /&gt;EDMA_0.TCD[2].NBYTES = 4; // 4 bytes per minor loop&lt;BR /&gt;EDMA_0.TCD[2].BITER = 8; // major iteration count - lenght of message&lt;BR /&gt;EDMA_0.TCD[2].CITER = 8; // major iteration count - lenght of message&lt;/P&gt;&lt;P&gt;/*** linking ***/&lt;BR /&gt;EDMA_0.TCD[2].CITERE_LINK = 0; // disabled&lt;BR /&gt;EDMA_0.TCD[2].BITERE_LINK = 0; // disabled&lt;BR /&gt;EDMA_0.TCD[2].MAJORE_LINK = 0; // disabled&lt;BR /&gt;EDMA_0.TCD[2].MAJORLINKCH = 0; // disabled&lt;/P&gt;&lt;P&gt;/*** others ***/&lt;BR /&gt;EDMA_0.TCD[2].D_REQ = 1; // do not disable channel when major loop is done&lt;BR /&gt;EDMA_0.TCD[2].INT_HALF = 0; // interrupt is not used&lt;BR /&gt;EDMA_0.TCD[2].INT_MAJ = 0; // interrupt is not used&lt;BR /&gt;EDMA_0.TCD[2].E_SG = 0; // disable scatter/gather operation&lt;BR /&gt;EDMA_0.TCD[2].BWC = 0; // default bandwidth control- no stalls&lt;BR /&gt;EDMA_0.TCD[2].START = 0;&lt;BR /&gt;EDMA_0.TCD[2].DONE = 0;&lt;BR /&gt;EDMA_0.TCD[2].ACTIVE = 0; // initialize status flags&lt;/P&gt;&lt;P&gt;EDMA_0.DMASERQ.R = 2; // enable the channel&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Thu, 24 Sep 2020 10:37:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1158612#M760</guid>
      <dc:creator>sachin_waghmare</dc:creator>
      <dc:date>2020-09-24T10:37:00Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Facing issue on implementing the eDMA with DSPI peripheral in MPC5675KRM microcontroller</title>
      <link>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159129#M764</link>
      <description>&lt;P&gt;Hi, your sample code omitted DMAMUX initialization, that is necessary. It is needed to enable channels and assign channel to DMA source request.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Sep 2020 06:58:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159129#M764</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2020-09-25T06:58:47Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Facing issue on implementing the eDMA with DSPI peripheral in MPC5675KRM microcontroller</title>
      <link>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159321#M765</link>
      <description>&lt;P&gt;Hi, I have been enabled the DMAMUX as follow,&lt;/P&gt;&lt;P&gt;DMAMUX_0.CHCONFIG[0].R = 0x00;&lt;BR /&gt;DMAMUX_0.CHCONFIG[0].R = 0x83;&lt;/P&gt;&lt;P&gt;to transmit data.&lt;/P&gt;</description>
      <pubDate>Fri, 25 Sep 2020 11:43:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159321#M765</guid>
      <dc:creator>sachin_waghmare</dc:creator>
      <dc:date>2020-09-25T11:43:19Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Facing issue on implementing the eDMA with DSPI peripheral in MPC5675KRM microcontroller</title>
      <link>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159325#M766</link>
      <description>&lt;P&gt;with the above mentioned code including the DMAMUX configuration.&amp;nbsp; I am getting the Destination write error though&amp;nbsp; EDMA_0.DMAES.R;&lt;/P&gt;&lt;P&gt;this register to solve that error the following things has been implemented in code,&lt;/P&gt;&lt;P&gt;PBRIDGE_0.MPROT0_7.B.MPROT2_MTW = 1;&lt;BR /&gt;PBRIDGE_0.MPROT0_7.B.MPROT2_MTR = 1;&lt;BR /&gt;PBRIDGE_0.PACR16_23.B.PACR17_SP = 0;&lt;BR /&gt;PBRIDGE_0.OPACR0_7.B.OPACR5_SP = 0;&lt;BR /&gt;PBRIDGE_0.OPACR16_23.B.OPACR23_SP = 0;&lt;/P&gt;&lt;P&gt;with this configuration, that error has been resolve, but still not getting the clock signal on the DSPI peripheral channel.&lt;/P&gt;&lt;P&gt;Kindly suggest the missed out things.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 25 Sep 2020 11:50:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/NXP-Designs/Re-Facing-issue-on-implementing-the-eDMA-with-DSPI-peripheral-in/m-p/1159325#M766</guid>
      <dc:creator>sachin_waghmare</dc:creator>
      <dc:date>2020-09-25T11:50:42Z</dc:date>
    </item>
  </channel>
</rss>

