topic P1022NXN2HFB ref clk in NXP Designs https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB-ref-clk/m-p/1051453#M433 <HTML><HEAD></HEAD><BODY><P><SPAN>Would you be able to tell me if the PCIe reference clock is needed if the PCIe system on the P1022NXN2HFB device is not beng used?</SPAN></P></BODY></HTML> Wed, 06 May 2020 16:23:06 GMT zachary_pecze 2020-05-06T16:23:06Z P1022NXN2HFB ref clk https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB-ref-clk/m-p/1051453#M433 <HTML><HEAD></HEAD><BODY><P><SPAN>Would you be able to tell me if the PCIe reference clock is needed if the PCIe system on the P1022NXN2HFB device is not beng used?</SPAN></P></BODY></HTML> Wed, 06 May 2020 16:23:06 GMT https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB-ref-clk/m-p/1051453#M433 zachary_pecze 2020-05-06T16:23:06Z Re: P1022NXN2HFB ref clk https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB-ref-clk/m-p/1051454#M434 <HTML><HEAD></HEAD><BODY><P>If a Serdes is not used, its reference clock is not needed.</P><P>Note that settings of cfg_serdes_ports[0:4] allow&nbsp; to disable Serdes1 or Serdes2 or both.</P><P></P><P>Regards,</P><P>Bulat</P></BODY></HTML> Fri, 08 May 2020 02:38:43 GMT https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB-ref-clk/m-p/1051454#M434 Bulat 2020-05-08T02:38:43Z