https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB/m-p/2289109#M1230 <P>Could you please confirm whether the PCIe reference clock is required if the PCIe subsystem on the P1022NXN2HFB device isn’t being used?</P> Wed, 07 Jan 2026 05:11:18 GMT MacOC 2026-01-07T05:11:18Z https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB/m-p/2289109#M1230 <P>Could you please confirm whether the PCIe reference clock is required if the PCIe subsystem on the P1022NXN2HFB device isn’t being used?</P> Wed, 07 Jan 2026 05:11:18 GMT https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB/m-p/2289109#M1230 MacOC 2026-01-07T05:11:18Z https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB/m-p/2290573#M1231 <P>If a Serdes is not used, its reference clock is not needed. Note that settings of cfg_serdes_ports [0:4] allow to disable Serdes1 or Serdes2 or both.</P> <P>Please refer to "18 SerDes Interface Pin Recommendations" in the attached document.</P> Fri, 09 Jan 2026 03:45:27 GMT https://community.nxp.com/t5/NXP-Designs/P1022NXN2HFB/m-p/2290573#M1231 yipingwang 2026-01-09T03:45:27Z