https://community.nxp.com/t5/NXP-Designs/ECC-Change-Regression-testing/m-p/1895964#M1151 <P>We have run into a regression on the ECU(SPC58NN84C3) that we believe is related to the changes for the ECE reset enablement.&nbsp; The issue we are seeing is the ECU(SPC58NN84C3) will continuously reset when jumping to the bootloader.&nbsp; The reset appears to be coming from the SBC (FS85),</P><P>The diagnostic from the SBC reads: upper 32 bits: 0xF920 and the lower 32 bits: 0x410000</P><P>&nbsp;</P><P>We have developed E2E ECC 1bit and 2bit error into sram, with FCCU channel configuration (EOUT signal Enable) and SBC configuration chnage FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB</P><P>E2EECC was called in 10ms tasks.</P><P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/13836">@petervlna</a>&nbsp; please support needed asap</P> Mon, 01 Jul 2024 12:52:56 GMT scnaidu 2024-07-01T12:52:56Z https://community.nxp.com/t5/NXP-Designs/ECC-Change-Regression-testing/m-p/1895964#M1151 <P>We have run into a regression on the ECU(SPC58NN84C3) that we believe is related to the changes for the ECE reset enablement.&nbsp; The issue we are seeing is the ECU(SPC58NN84C3) will continuously reset when jumping to the bootloader.&nbsp; The reset appears to be coming from the SBC (FS85),</P><P>The diagnostic from the SBC reads: upper 32 bits: 0xF920 and the lower 32 bits: 0x410000</P><P>&nbsp;</P><P>We have developed E2E ECC 1bit and 2bit error into sram, with FCCU channel configuration (EOUT signal Enable) and SBC configuration chnage FS8X_FS_I_FCCU12_FS_IMPACT_FS0B_RSTB</P><P>E2EECC was called in 10ms tasks.</P><P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/13836">@petervlna</a>&nbsp; please support needed asap</P> Mon, 01 Jul 2024 12:52:56 GMT https://community.nxp.com/t5/NXP-Designs/ECC-Change-Regression-testing/m-p/1895964#M1151 scnaidu 2024-07-01T12:52:56Z