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    <title>topic Typo's in PN7462 phhalCt module in NFC</title>
    <link>https://community.nxp.com/t5/NFC/Typo-s-in-PN7462-phhalCt-module/m-p/938606#M5800</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;While experimenting with the CT interface of the PN7462 I encoutered some typo's and double defined declarations that I want to share with you:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define&amp;nbsp;PHHAL_CT_CARD_DEFAULT_CLOCK is defined in&amp;nbsp;phhalCt_Int.h and&amp;nbsp;phhalCt_Common.c&lt;/P&gt;&lt;P&gt;Luckily with the same value and afterall only used within&amp;nbsp;phhalCt_Common.c.&lt;/P&gt;&lt;P&gt;In the end it should be defined only once is my advise.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Furthermore in both files the comment that goes with it mentions:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/** Macro for Default clock value &lt;STRONG&gt;4.92MHz&lt;/STRONG&gt; for activation.*/&lt;BR /&gt;#define PHHAL_CT_CARD_DEFAULT_CLOCK 0x05&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Since the crystal is 27.12MHZ and 0x05 means Fclk/6 it is actually &lt;STRONG&gt;4.52MHz&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And in the file&amp;nbsp;&lt;SPAN&gt;phhalCt_Common.c the following comment can be found within&amp;nbsp;phhalCt_SetTimer():&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* Load the default values of ETU */&lt;BR /&gt; /* Set the card clock default value to 5 Mhz max */&lt;BR /&gt; PH_REG_SET_FIELD(CT_CCRx_REG, ACC2_ACC0 ,PHHAL_CT_CARD_DEFAULT_CLOCK);&lt;BR /&gt; /* The PDR default value 372 is multiplied by 8 will result in 0xBA0, Since we are dividing the Card clock&lt;BR /&gt; * frequency &lt;STRONG&gt;by 8&lt;/STRONG&gt; [ACC2- ACC0 = clock/6], we have to multiply the default 372 etu value with &lt;STRONG&gt;8&lt;/STRONG&gt; for sampling and&lt;BR /&gt; * hence the value 0x8B8 is loaded as the default value in the PDR register */&lt;BR /&gt; PH_REG_SET(CT_PDRx_LSB_REG, 0xB8);&lt;BR /&gt; PH_REG_SET(CT_PDRx_MSB_REG, 0x08);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;'&lt;STRONG&gt;by 8&lt;/STRONG&gt;' and '&lt;STRONG&gt;8&lt;/STRONG&gt;' should actually be '&lt;STRONG&gt;by 6&lt;/STRONG&gt;' and '&lt;STRONG&gt;6&lt;/STRONG&gt;' since 372 * 6 = 0x8B8&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Robert&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 18 Oct 2019 12:05:36 GMT</pubDate>
    <dc:creator>roberto74</dc:creator>
    <dc:date>2019-10-18T12:05:36Z</dc:date>
    <item>
      <title>Typo's in PN7462 phhalCt module</title>
      <link>https://community.nxp.com/t5/NFC/Typo-s-in-PN7462-phhalCt-module/m-p/938606#M5800</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;While experimenting with the CT interface of the PN7462 I encoutered some typo's and double defined declarations that I want to share with you:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define&amp;nbsp;PHHAL_CT_CARD_DEFAULT_CLOCK is defined in&amp;nbsp;phhalCt_Int.h and&amp;nbsp;phhalCt_Common.c&lt;/P&gt;&lt;P&gt;Luckily with the same value and afterall only used within&amp;nbsp;phhalCt_Common.c.&lt;/P&gt;&lt;P&gt;In the end it should be defined only once is my advise.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Furthermore in both files the comment that goes with it mentions:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/** Macro for Default clock value &lt;STRONG&gt;4.92MHz&lt;/STRONG&gt; for activation.*/&lt;BR /&gt;#define PHHAL_CT_CARD_DEFAULT_CLOCK 0x05&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Since the crystal is 27.12MHZ and 0x05 means Fclk/6 it is actually &lt;STRONG&gt;4.52MHz&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And in the file&amp;nbsp;&lt;SPAN&gt;phhalCt_Common.c the following comment can be found within&amp;nbsp;phhalCt_SetTimer():&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* Load the default values of ETU */&lt;BR /&gt; /* Set the card clock default value to 5 Mhz max */&lt;BR /&gt; PH_REG_SET_FIELD(CT_CCRx_REG, ACC2_ACC0 ,PHHAL_CT_CARD_DEFAULT_CLOCK);&lt;BR /&gt; /* The PDR default value 372 is multiplied by 8 will result in 0xBA0, Since we are dividing the Card clock&lt;BR /&gt; * frequency &lt;STRONG&gt;by 8&lt;/STRONG&gt; [ACC2- ACC0 = clock/6], we have to multiply the default 372 etu value with &lt;STRONG&gt;8&lt;/STRONG&gt; for sampling and&lt;BR /&gt; * hence the value 0x8B8 is loaded as the default value in the PDR register */&lt;BR /&gt; PH_REG_SET(CT_PDRx_LSB_REG, 0xB8);&lt;BR /&gt; PH_REG_SET(CT_PDRx_MSB_REG, 0x08);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;'&lt;STRONG&gt;by 8&lt;/STRONG&gt;' and '&lt;STRONG&gt;8&lt;/STRONG&gt;' should actually be '&lt;STRONG&gt;by 6&lt;/STRONG&gt;' and '&lt;STRONG&gt;6&lt;/STRONG&gt;' since 372 * 6 = 0x8B8&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Robert&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 18 Oct 2019 12:05:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/NFC/Typo-s-in-PN7462-phhalCt-module/m-p/938606#M5800</guid>
      <dc:creator>roberto74</dc:creator>
      <dc:date>2019-10-18T12:05:36Z</dc:date>
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