UART as host interface for CLRC663

lokeshjassal2004 — Sun, 25 Jan 2026 16:23:54 GMT

Hi NXP Community,

I am experiencing an issue where my CLRC663 plus is not responding over the UART interface, and I would appreciate any insights into what might be missing from my configuration.

Problem Description:

Despite sending valid frames to the RX pin, the CLRC663 TX pin (Pin 30) remains idle (no signal transition).

Current Setup & Troubleshooting Steps:

Power & Clock: I have verified the device is not in Power Down (PDOWN) state. All power supplies are stable, and the oscillator is functioning correctly.
Interface Selection: Pins IFSEL0 and IFSEL1 are both tied to VSS, which according to the datasheet, selects the UART interface.
Physical Layer:
- Pin 31 (IF3): Connected to PAD_VDD (3.3V) as required per the CLRC663 Datasheet.
- Logic Levels: Verified 3.3V for High and 0V for Low on all digital lines.
Signal Analysis: I have attached oscilloscope plots for Pin 28 (RX) and Pin 30 (TX).
- The RX plot shows a valid command to read register 0x3D (PLL_Ctrl Register) at the baud rate of 115.34 kbps, which is close to default rate of 115.2kbps.
- The TX plot shows no response from the CLRC663; the line remains consistently high.

Question:
Since the interface pins (IFSEL) and power levels are correctly configured for UART, is there a specific startup sequence or internal reset condition required before the CLRC663 begins monitoring the UART RX line?

Any help would be greatly appreciated.

Regards,
Lokesh Jassal

Re: UART as host interface for CLRC663

jimmychan — Thu, 05 Feb 2026 03:20:33 GMT

Please read the 8.4.3 RS232 interface in the datasheet.

FYI.

CLRC663 Programming Guide via UART - NXP Community

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UART as host interface for CLRC663

Re: UART as host interface for CLRC663