NFCのトピックCLRC663 layout on a multilayer stack

CLRC663 layout on a multilayer stack

dramos — Wed, 16 Jul 2025 05:47:40 GMT

Hi to all,

I am designing a 6 layer pcb with the #CLRC663. After reading the Application Note AN11019 (rev 1.5), in the chapter 3.2 Layout recommendation there is a mention about the GND plane under the CLRC663 evaluation board. The GND plane is in middle layer of the board

On the SW4301 - CLEV6630B v2.0 PCB,there is not copper under the matching circuitry.

As I mentioned before, I have a multilayer board and I would like to know if I can place a GND plane under the matching components (Matching components Layer1-GND Layer2). Can I have traces under the matching components in the other layers? For example layer 3 or Layer 6?

Or should I remove all the copper under the matching components in all layers of my stack?

Thanks for your comments.

david

Re: CLRC663 layout on a multilayer stack

Tomas_Parizek — Wed, 16 Jul 2025 06:00:33 GMT

Hello @dramos

We typically keep a first GND layer under matching as shown below. This is mainly due to EMI reasons.

Tomas

Re: CLRC663 layout on a multilayer stack

dramos — Wed, 16 Jul 2025 09:56:36 GMT

Hi Tomas,

Firstly thanks for your response.

If below the matching circuit I place a GND plane for EMI control , is it necessary to remove the copper area in the rest of the layers?

In my case I am using a 6 layers stack, if the matching is in the first layer and the GND in the second I think that I shouldn't remove the copper on the other four layers. The demo board is not made in that way and I cannot understand why.

Any idea about the best procedure?

Thanks to all

david