topic Re: Disabling the MPC5554/e200z6 cache in MPC5xxx

Disabling the MPC5554/e200z6 cache

ricardofranca — Thu, 19 Nov 2015 09:37:16 GMT

Hello,

While playing with the MPC5554 cache configuration, I am measuring execution times when running some code with several cache configurations. At some point, I tried to deactivate the cache using two different approaches (my code snippets use Green Hills asm syntax):

i) Using the last bit of L1CSR0

__asmleaf void turn_cache_off() {

mfspr r3, l1csr0

clrrwi r3, r3, 1

msync

isync

mtspr l1csr0, r3

isync

}

ii) Flushing/invalidating the entire cache, then disabling line replacement in all its ways

ii-1) Flush+invalidate

__asmleaf void flush_inv_cache_line(uint32_t flushed_way, uint32_t flushed_set) {

%reg flushed_way %reg flushed_set

mfspr r3, l1finv0

insrwi r3, flushed_way, 5, 3

insrwi r3, flushed_set, 7, 20

li r4, 2

rlwimi r3, r4, 0, 30, 31

msync

mtspr l1finv0, r3

}

void flush_inv_cache(void) {

uint32_t i;

uint32_t j;

for (i = 0u; i < 8u; i++)

{

for (j = 0u; j < 128u; j++)

{

flush_inv_cache_line(i, j);

}

ii-2) Disabling line replacement

__asmleaf void turn_icache_off() {

mfspr r3, l1csr0

li r4, 15

insrwi r3, r4, 4, 0

li r4, 1

insrwi r3, r4, 1, 8

msync

isync

mtspr l1csr0, r3

isync

}

__asmleaf void turn_dcache_off() {

mfspr r3, l1csr0

li r4, 15

insrwi r3, r4, 4, 4

li r4, 1

insrwi r3, r4, 1, 9

msync

isync

mtspr l1csr0, r3

isync

}

It seems that my code runs faster with the second approach, which gives me the impression that somehow there is still cache activity somewhere. Do you know what is missing for me to have the same timing behavior in both cases?

Best regards,

Ricardo

Re: Disabling the MPC5554/e200z6 cache

davidtosenovjan — Thu, 19 Nov 2015 12:49:09 GMT

- I am not sure which two point you are comparing together? ‘ii-1’ vs. ‘ii-2’ that is ‘Flush+invalidate’ vs. ‘Disabling line replacement’?

- MPC5554 has one unified cache, but your code turns icache off and turns dcache off?

- are you using copy-back or write-through mode?

Re: Disabling the MPC5554/e200z6 cache

ricardofranca — Thu, 19 Nov 2015 15:00:07 GMT

Hi David,

Thanks for your quick reply.

- I am trying to compare i) versus (ii-1 + ii-2). However, I think I shall actually compare (ii-1 + i) versus (ii-1 + ii-2) - I just noticed that disabling the cache without flushing it yields some strange timing behavior.

- Since the last bit of L1CSR0 disables the unified cache for both instructions and data, I was trying to make it data-only or instruction-only by disabling cache ways for instruction or data replacement.

- I am using copy-back mode.

Maybe I was not too clear in my question: I would like to know if (after a cache flush/invalidate) disabling it via L1CSR0[CE] or disabling all its ways for line replacement are equivalent ways of turning the cache off.

Best regards,

Re: Disabling the MPC5554/e200z6 cache

davidtosenovjan — Fri, 20 Nov 2015 12:40:17 GMT

Pay attention to erratum e3421 (page 25) - cannot this be the reason of your issue?

http://cache.freescale.com/files/32bit/doc/errata/MPC5554_REVB.pdf

Re: Disabling the MPC5554/e200z6 cache

ricardofranca — Wed, 18 May 2022 11:28:43 GMT

Hello,

After all these years, I must find my old hardware to run the code again, but this erratum looks very consistent with the behavior I had described. Thanks a lot for your answer!