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    <title>topic MPC5xMUC FlexCAN Tx and Rx interrupt question in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711274#M9292</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I&amp;nbsp;want to konw &amp;nbsp;MPC5744 FlexCAN&amp;nbsp;module hasn't &lt;SPAN&gt;a send completion entry interrupt function and a receive completion entry interrupt function?&lt;/SPAN&gt; &amp;nbsp;&lt;/P&gt;&lt;P&gt;I through computer software to send a standard data frame to my evaluate board , I through check interrupt flag to read data. But i &lt;SPAN&gt;want to process the receive data &amp;nbsp;by receiving interrupts,&lt;/SPAN&gt; I set FlexCAN Interrupt mask regiseter to enable interrupt receive&amp;nbsp;function. But this code is not triggle interrupt function,t&lt;SPAN&gt;he corresponding interrupt register is already in set 1.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 20 Oct 2017 08:02:08 GMT</pubDate>
    <dc:creator>大大许</dc:creator>
    <dc:date>2017-10-20T08:02:08Z</dc:date>
    <item>
      <title>MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711274#M9292</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I&amp;nbsp;want to konw &amp;nbsp;MPC5744 FlexCAN&amp;nbsp;module hasn't &lt;SPAN&gt;a send completion entry interrupt function and a receive completion entry interrupt function?&lt;/SPAN&gt; &amp;nbsp;&lt;/P&gt;&lt;P&gt;I through computer software to send a standard data frame to my evaluate board , I through check interrupt flag to read data. But i &lt;SPAN&gt;want to process the receive data &amp;nbsp;by receiving interrupts,&lt;/SPAN&gt; I set FlexCAN Interrupt mask regiseter to enable interrupt receive&amp;nbsp;function. But this code is not triggle interrupt function,t&lt;SPAN&gt;he corresponding interrupt register is already in set 1.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Oct 2017 08:02:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711274#M9292</guid>
      <dc:creator>大大许</dc:creator>
      <dc:date>2017-10-20T08:02:08Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711275#M9293</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Make certain you're clearing the interrupt and also 'New data in buffer' flags by writing a '1' to the relevant register bit&amp;nbsp;to clear it. Only by doing this will you know whether you're getting a new message or re-processing an old one.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Oct 2017 09:27:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711275#M9293</guid>
      <dc:creator>aero72</dc:creator>
      <dc:date>2017-10-20T09:27:16Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711276#M9294</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I'm sure that the corresponding flag bits in the interrupt flag register are clear, and I'm sure that the data received by querying is up to date, not the previous one&lt;/SPAN&gt;.&lt;/P&gt;&lt;P&gt;The code received a standard data frame by compute software ,the relevant interrupt mask register bit is enable ,and &amp;nbsp;relevant interrupt flag register&amp;nbsp;is set.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The program does not perform interrupt subroutines&lt;/SPAN&gt; .&lt;/P&gt;&lt;P&gt;thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Oct 2017 12:38:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711276#M9294</guid>
      <dc:creator>大大许</dc:creator>
      <dc:date>2017-10-20T12:38:03Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711277#M9295</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;FlexCAN interrupt setting is follow&lt;/P&gt;&lt;P&gt;INTC_0.PSR[524].B.PRIN&amp;nbsp; =&amp;nbsp; INT_CAN_PRIORITY;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //CAN ISR IRQ CPU degree&lt;/P&gt;&lt;P&gt;&amp;nbsp;CAN[nbModule]-&amp;gt;IMASK2.R = 0x00000000;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //FlexCAN module&lt;BR /&gt;&amp;nbsp;CAN[nbModule]-&amp;gt;IMASK1.R = 0x00F00000;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //set MB[8] receive interrupt and MB[9] send interrupt&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is there anything wrong with my setup?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 21 Oct 2017 08:16:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711277#M9295</guid>
      <dc:creator>大大许</dc:creator>
      <dc:date>2017-10-21T08:16:04Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711278#M9296</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;CAN[nbModule]-&amp;gt;IMASK1.R = 0x00F00000;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; does not enable MB8 and MB9 interrupt. In fact it enables MB23-MB20 interrupts.&lt;/P&gt;&lt;P&gt;You should use CAN[nbModule]-&amp;gt;IMASK1.R = 0x00000300;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //set MB[8] receive interrupt and MB[9] send interrupt&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Petr&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Oct 2017 06:21:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711278#M9296</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2017-10-23T06:21:22Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711279#M9297</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;5744中的can通信，你处理过接收端可以让接收端一对多通信吗？&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Oct 2017 00:33:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711279#M9297</guid>
      <dc:creator>wongdavid</dc:creator>
      <dc:date>2017-10-25T00:33:15Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5xMUC FlexCAN Tx and Rx interrupt question</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711280#M9298</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;5744中CAN通信，接收多个不同messgeID的模式（接收端一对多通信），你能成功吗？我没搞定&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 15 Jan 2018 03:23:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5xMUC-FlexCAN-Tx-and-Rx-interrupt-question/m-p/711280#M9298</guid>
      <dc:creator>剑明肖</dc:creator>
      <dc:date>2018-01-15T03:23:20Z</dc:date>
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