topic Re: MPC5777C etpu phase error in MPC5xxx

MPC5777C etpu phase error

baimingshao — Mon, 28 Aug 2017 13:04:05 GMT

Hi All,

I have a question regarding the MPC5777C etpu. What I did is following:

I downloaded the eTPU pwmmac function from eTPU Function Selector, config it with graphical configuration tool. I use TCR1 as the clock of engine A, set channel 0 as a master of a 1-phase output, channel 1 as the output PWM signals. Besides that, I also add another 1-phase PWM output, using channel 2 as master, and channel 3 as PWM signals. Both of these two PWM functions are left edge aligned.

Since channels are using the same clock, and are both in engine A, I would assume the output of channel 1 and channel 3 are always left edge aligned. However, at power up, there is always a phase error between these two. But if I reset the CPU using either the debugger, or the hardware pin, the phase error is gone.

Any idea?

Thanks,

Re: MPC5777C etpu phase error

davidtosenovjan — Tue, 29 Aug 2017 10:39:47 GMT

Hi,

is the delay of fixed length? I suppose it is certain multiple TCR1 period, is it?

Re: MPC5777C etpu phase error

baimingshao — Tue, 29 Aug 2017 15:39:34 GMT

Hi David,

Thanks for the reply. It is randomly every time I power up. I cannot tell if it is multiple of TCR1, since I am running at 100MHz, each period is very small.

Just a thought, could it because of the etpu code flash problem? To me, it looks like the etpu code started before everything is copied to etpu code ram. But if I do the reset, since all the code is still in the ram which is copied from last power up, it works? But I am using the library, and there is no change on this part.

Following is my code, all these etpu related functions are from the library without any change:

int main(void) {
int counter = 0;

//setup clock
Sysclk_Setup(SELECT_SYSCLK_PLL0, 1, 2, 2, 2, SELECT_PLL0_SOURCE_XOSC, 5);

//eTPU
GPIO_Init(115, PRIMARY_FUN, 0, 1); //etupa 1 ~ 7
GPIO_Init(116, PRIMARY_FUN, 0, 1);
GPIO_Init(117, PRIMARY_FUN, 0, 1);
GPIO_Init(118, PRIMARY_FUN, 0, 1);
GPIO_Init(119, PRIMARY_FUN, 0, 1);
GPIO_Init(120, PRIMARY_FUN, 0, 1);
GPIO_Init(121, PRIMARY_FUN, 0, 1);
GPIO_Init(122, PRIMARY_FUN, 0, 1); //etupa 8,9
GPIO_Init(123, PRIMARY_FUN, 0, 1);

GPIO_Init(142, PRIMARY_FUN, 0, 1); //etpua 31, 28
GPIO_Init(145, PRIMARY_FUN, 0, 1);

my_system_etpu_init();

my_system_etpu_start();

fs_etpu_pwmmac_enable_3ph(PWMMAC0_MASTER, FS_ETPU_PWMMAC_ACTIVE_HIGH,
FS_ETPU_PWMMAC_ACTIVE_LOW);
fs_etpu_pwmmac_update_duty_cycles(PWMMAC0_MASTER, 0x7fffff, 0x7fffff,
0x7fffff);

fs_etpu_pwmmac_enable_1ph( PWMMAC1_MASTER,
FS_ETPU_PWMMAC_ACTIVE_HIGH,
FS_ETPU_PWMMAC_ACTIVE_LOW);
fs_etpu_pwmmac_update_duty_cycles(PWMMAC1_MASTER, 0x7fffff, 0, 0);

xcptn_xmpl(); /* Configure and Enable Interrupts */

/* Loop forever */
for (;;) {
counter++;
}
}

Thanks,

Baiming