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    <title>MPC5xxx中的主题 Re: MPC5777M peripheral core isync</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5777M-peripheral-core-isync/m-p/676016#M7948</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, se_isync is correct syntax.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 06 Jun 2017 08:39:22 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2017-06-06T08:39:22Z</dc:date>
    <item>
      <title>MPC5777M peripheral core isync</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5777M-peripheral-core-isync/m-p/676015#M7947</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm trying to use the &lt;SPAN&gt;GetResource&lt;/SPAN&gt; example on the peripheral core of the MPC5777M, but I get a compiler error that isync is not available in VLE mode - "Error: Illegal instruction for VLE mode: `isync'"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;GetResource:&lt;BR /&gt;wrteei 0 # disable external interrupts to the Processor&lt;BR /&gt;raise PRI # Write to CPR, cache inhibit, guarded&lt;BR /&gt;mbar # flush out writes from store buffer&lt;BR /&gt;wrteei 1 # enable external interrupts to the Processor&lt;BR /&gt;isync # re-fetch Processor pipeline&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there&amp;nbsp;a way to build in bookE mode for the e200z4 on the 77M? Or is there a different instruction I should be using to force instruction sync?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Jacob&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EDIT, did more research:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Is the correct instruction&amp;nbsp;se_isync?&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 01:27:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5777M-peripheral-core-isync/m-p/676015#M7947</guid>
      <dc:creator>jschloss</dc:creator>
      <dc:date>2017-06-06T01:27:44Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5777M peripheral core isync</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5777M-peripheral-core-isync/m-p/676016#M7948</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, se_isync is correct syntax.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Jun 2017 08:39:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5777M-peripheral-core-isync/m-p/676016#M7948</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2017-06-06T08:39:22Z</dc:date>
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