https://community.nxp.com/t5/MPC5xxx/Query-on-MPC5777C-ERM-module-functionality/m-p/659321#M7176 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I am trying to test the functionality of MPC5777C EIM(Error Injection Module) and ERM(Error Reporting Module). I have configured to inject errors in the PRAMC_0 and PRAMC_1 channels in the EIM. When I am doing a read access in System RAM at address 0x4000_0000(the memory controlled by PRAMC_0), I would expect that an error be reported in the PRAMC_0 channel in the ERM. However, I am seeing that the error is being reported in the "Core0 data" or "Core1 data" channels(channel numbers: 14,16) in the ERM depending on where my build is loaded and not in the PRAMC_0 channel. On the other hand, when I do a write to the memory, I could see errors being reported in the PRAMC channel in the ERM and nothing reported in "Core data" channels. Could you please explain the reason for this behaviour?</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Regards,</P><P>Sidhartha.</P></BODY></HTML> Wed, 22 Feb 2017 06:58:33 GMT sidharthachittu 2017-02-22T06:58:33Z https://community.nxp.com/t5/MPC5xxx/Query-on-MPC5777C-ERM-module-functionality/m-p/659321#M7176 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I am trying to test the functionality of MPC5777C EIM(Error Injection Module) and ERM(Error Reporting Module). I have configured to inject errors in the PRAMC_0 and PRAMC_1 channels in the EIM. When I am doing a read access in System RAM at address 0x4000_0000(the memory controlled by PRAMC_0), I would expect that an error be reported in the PRAMC_0 channel in the ERM. However, I am seeing that the error is being reported in the "Core0 data" or "Core1 data" channels(channel numbers: 14,16) in the ERM depending on where my build is loaded and not in the PRAMC_0 channel. On the other hand, when I do a write to the memory, I could see errors being reported in the PRAMC channel in the ERM and nothing reported in "Core data" channels. Could you please explain the reason for this behaviour?</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Regards,</P><P>Sidhartha.</P></BODY></HTML> Wed, 22 Feb 2017 06:58:33 GMT https://community.nxp.com/t5/MPC5xxx/Query-on-MPC5777C-ERM-module-functionality/m-p/659321#M7176 sidharthachittu 2017-02-22T06:58:33Z https://community.nxp.com/t5/MPC5xxx/Query-on-MPC5777C-ERM-module-functionality/m-p/659322#M7177 <HTML><HEAD></HEAD><BODY><P>EIM injects error to the particular RAM array bus, so it is being detected by the side affected by this error.</P><P>If it is write (thus transfer from Core0 to PRAMC_0 with error on the way), it’ll be detected by PRAMC_0.</P><P>If it is read (thus transfer from PRAMC_0 to Core0 with error on the way), it’ll be detected by Core0.</P><P>&nbsp;</P><P>If you see more errors in more ERM channels at once, if could be possibly caused by enabled cache memory.</P></BODY></HTML> Wed, 22 Feb 2017 15:53:53 GMT https://community.nxp.com/t5/MPC5xxx/Query-on-MPC5777C-ERM-module-functionality/m-p/659322#M7177 davidtosenovjan 2017-02-22T15:53:53Z