MPC5xxx中的主题 Re: MPC5604E Clock Architecture Issues https://community.nxp.com/t5/MPC5xxx/MPC5604E-Clock-Architecture-Issues/m-p/657912#M7130 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P>I have confirmed the same behavior on my board. Yes, the input for clk_out is before the divider. Thanks for pointing this out, I will report it.</P><P></P><P>Yes, it is possible that the clk out can be set to higher frequencies but we do not guarantee the functionality of the device in this case. It's out of our specification.</P><P></P><P>Regards,</P><P>Lukas</P></BODY></HTML> Tue, 15 Nov 2016 14:06:08 GMT lukaszadrapa 2016-11-15T14:06:08Z MPC5604E Clock Architecture Issues https://community.nxp.com/t5/MPC5xxx/MPC5604E-Clock-Architecture-Issues/m-p/657911#M7129 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I'm working on MPC5604E, and wanted to get clock out of "clk_out" pin [PCR36, Pin No. 62], according to Clock Architecture Block diagram [Refer "Img1"], Input to the "clk_out" pad is from FMPLL_0 after FMPLL_CLK_DIV, But according to over experimentation its not the case, according to what I have validated the input to "clk_out" is from FMPLL_0 before FMPLL_CLK_DIV. It also says maximum frequency supported on "clk_out" pad is 32MHz [Refer Img2]</P><P>but we have tested it upto 120MHz. Do clarify the issues.</P><P><span class="lia-inline-image-display-wrapper"><img src="https://community.nxp.com/t5/image/serverpage/image-id/122501iCF51E1752F0A315A/image-size/large?v=v2&amp;px=999" title="169441_169441.png" alt="169441_169441.png" /></span><span class="lia-inline-image-display-wrapper"><img src="https://community.nxp.com/t5/image/serverpage/image-id/8755iC3A576A45A93876A/image-size/large?v=v2&amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P><span class="lia-inline-image-display-wrapper"><img src="https://community.nxp.com/t5/image/serverpage/image-id/122502iA0E13FBB19AE8161/image-size/large?v=v2&amp;px=999" title="169445_169445.png" alt="169445_169445.png" /></span><span class="lia-inline-image-display-wrapper"><img src="https://community.nxp.com/t5/image/serverpage/image-id/8878i1018F5867937C014/image-size/large?v=v2&amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Thanks &amp; Regards&nbsp;</P><P>SUHAS S</P></BODY></HTML> Mon, 14 Nov 2016 15:10:06 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604E-Clock-Architecture-Issues/m-p/657911#M7129 suhass 2016-11-14T15:10:06Z Re: MPC5604E Clock Architecture Issues https://community.nxp.com/t5/MPC5xxx/MPC5604E-Clock-Architecture-Issues/m-p/657912#M7130 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P>I have confirmed the same behavior on my board. Yes, the input for clk_out is before the divider. Thanks for pointing this out, I will report it.</P><P></P><P>Yes, it is possible that the clk out can be set to higher frequencies but we do not guarantee the functionality of the device in this case. It's out of our specification.</P><P></P><P>Regards,</P><P>Lukas</P></BODY></HTML> Tue, 15 Nov 2016 14:06:08 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604E-Clock-Architecture-Issues/m-p/657912#M7130 lukaszadrapa 2016-11-15T14:06:08Z